SNVSA21G May   2014  – October 2017 LP8860-Q1

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Current Sinks Electrical Characteristics
    7. 7.7  Boost Converter Characteristics
    8. 7.8  Logic Interface Characteristics
    9. 7.9  VIN Undervoltage Protection (VIN_UVLO)
    10. 7.10 VDD Undervoltage Protection (VDD_UVLO)
    11. 7.11 VIN Overvoltage Protection (VIN_OVP)
    12. 7.12 VIN Overcurrent Protection (VIN_OCP)
    13. 7.13 Power-Line FET Control Electrical Characteristics
    14. 7.14 External Temp Sensor Control Electrical Characteristics
    15. 7.15 I2C Serial Bus Timing Parameters (SDA, SCLK)
    16. 7.16 SPI Timing Requirements
    17. 7.17 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
      1. 8.1.1 Boost Controller
      2. 8.1.2 LED Output Configurations
      3. 8.1.3 Display Mode
      4. 8.1.4 Cluster Mode
      5. 8.1.5 Hybrid Dimming
      6. 8.1.6 Charge Pump and Square Waveform (SQW) Output
      7. 8.1.7 Power-Line FET
      8. 8.1.8 Protection Features
      9. 8.1.9 Advanced Thermal Protection Features
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Clock Generation
        1. 8.3.1.1 LED PWM Clock Generation With VSYNC
        2. 8.3.1.2 LED PWM Frequency and Resolution
      2. 8.3.2 Brightness Control (Display Mode)
        1. 8.3.2.1 PWM Input Duty Cycle Based Control
        2. 8.3.2.2 Brightness Register Control
        3. 8.3.2.3 PWM Input Duty × Brightness Register
        4. 8.3.2.4 PWM-Input Direct Control
        5. 8.3.2.5 Brightness Slope
        6. 8.3.2.6 LED Dimming Methods
        7. 8.3.2.7 PWM Calculation Data Flow for Display Mode
      3. 8.3.3 LED Output Modes and Phase Shift PWM (PSPWM) Scheme
      4. 8.3.4 LED Current Setting
      5. 8.3.5 Cluster Mode
      6. 8.3.6 Boost Controller
      7. 8.3.7 Charge Pump
      8. 8.3.8 Powerline Control FET
      9. 8.3.9 Protection and Fault Detection Modes
        1. 8.3.9.1 LED Fault Comparators and Adaptive Boost Control
        2. 8.3.9.2 LED Current Dimming With Internal Temperature Sensor
        3. 8.3.9.3 LED Current Limitation With External NTC Sensor
        4. 8.3.9.4 LED Current Dimming With External NTC Sensor
        5. 8.3.9.5 Protection Feature and Fault Summary
    4. 8.4 Device Functional Modes
      1. 8.4.1 Standby Mode
      2. 8.4.2 Active Mode
      3. 8.4.3 Fault Recovery State
      4. 8.4.4 Start-Up and Shutdown Sequences
    5. 8.5 Programming
      1. 8.5.1 EEPROM
      2. 8.5.2 Serial Interface
        1. 8.5.2.1 SPI Interface
        2. 8.5.2.2 I2C Serial Bus Interface
          1. 8.5.2.2.1 Interface Bus Overview
          2. 8.5.2.2.2 Data Transactions
          3. 8.5.2.2.3 Acknowledge Cycle
          4. 8.5.2.2.4 Acknowledge After Every Byte Rule
          5. 8.5.2.2.5 Addressing Transfer Formats
          6. 8.5.2.2.6 Control Register Write Cycle
          7. 8.5.2.2.7 Control Register Read Cycle
    6. 8.6 Register Maps
      1. 8.6.1 Register Bit Explanations
        1. 8.6.1.1  Display/Cluster1 Brightness Control MSB
        2. 8.6.1.2  Display/Cluster1 Brightness Control LSB
        3. 8.6.1.3  Display/Cluster1 Output Current MSB
        4. 8.6.1.4  Display/Cluster1 Output Current LSB
        5. 8.6.1.5  Cluster2 Brightness Control MSB
        6. 8.6.1.6  Cluster2 Brightness Control LSB
        7. 8.6.1.7  Cluster2 Output Current
        8. 8.6.1.8  Cluster3 Brightness Control MSB
        9. 8.6.1.9  Cluster3 Brightness Control LSB
        10. 8.6.1.10 Cluster3 Output Current
        11. 8.6.1.11 Cluster4 Brightness Control MSB
        12. 8.6.1.12 Cluster4 Brightness Control LSB
        13. 8.6.1.13 Cluster4 Output Current
        14. 8.6.1.14 Configuration
        15. 8.6.1.15 Status
        16. 8.6.1.16 Fault
        17. 8.6.1.17 LED Fault
        18. 8.6.1.18 Fault Clear
        19. 8.6.1.19 Identification
        20. 8.6.1.20 Temp MSB
        21. 8.6.1.21 Temp LSB
        22. 8.6.1.22 Display LED Current MSB
        23. 8.6.1.23 Display LED Current LSB
        24. 8.6.1.24 Display LED PWM MSB
        25. 8.6.1.25 Display LED PWM LSB
        26. 8.6.1.26 EEPROM Control
        27. 8.6.1.27 EEPROM Unlock Code
      2. 8.6.2 EEPROM Bit Explanations
        1. 8.6.2.1  EEPROM Register 0
        2. 8.6.2.2  EEPROM Register 1
        3. 8.6.2.3  EEPROM Register 2
        4. 8.6.2.4  EEPROM Register 3
        5. 8.6.2.5  EEPROM Register 4
        6. 8.6.2.6  EEPROM Register 5
        7. 8.6.2.7  EEPROM Register 6
        8. 8.6.2.8  EEPROM Register 7
        9. 8.6.2.9  EEPROM Register 8
        10. 8.6.2.10 EEPROM Register 9
        11. 8.6.2.11 EEPROM Register 10
        12. 8.6.2.12 EEPROM Register 11
        13. 8.6.2.13 EEPROM Register 12
        14. 8.6.2.14 EEPROM Register 13
        15. 8.6.2.15 EEPROM Register 14
        16. 8.6.2.16 EEPROM Register 15
        17. 8.6.2.17 EEPROM Register 16
        18. 8.6.2.18 EEPROM Register 17
        19. 8.6.2.19 EEPROM Register 18
        20. 8.6.2.20 EEPROM Register 19
        21. 8.6.2.21 EEPROM Register 20
        22. 8.6.2.22 EEPROM Register 21
        23. 8.6.2.23 EEPROM Register 22
        24. 8.6.2.24 EEPROM Register 23
        25. 8.6.2.25 EEPROM Register 24
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Typical Application for Display Backlight
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1  Inductor Selection
          2. 9.2.1.2.2  Output Capacitor Selection
          3. 9.2.1.2.3  Input Capacitor Selection
          4. 9.2.1.2.4  Charge Pump Output Capacitor
          5. 9.2.1.2.5  Charge Pump Flying Capacitor
          6. 9.2.1.2.6  Diode
          7. 9.2.1.2.7  Boost Converter Transistor
          8. 9.2.1.2.8  Boost Sense Resistor
          9. 9.2.1.2.9  Power Line Transistor
          10. 9.2.1.2.10 Input Current Sense Resistor
          11. 9.2.1.2.11 Filter Component Values
            1. 9.2.1.2.11.1 Critical Components for Design
        3. 9.2.1.3 Application Performance Plots
      2. 9.2.2 Low VDD Voltage and Combined Output Mode Application
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Performance Plots
      3. 9.2.3 High Output Voltage Application
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Performance Plots
      4. 9.2.4 High Output Current Application
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
        3. 9.2.4.3 Application Performance Plots
      5. 9.2.5 Three-Channel Configuration Without Serial Interface
        1. 9.2.5.1 Design Requirements
        2. 9.2.5.2 Detailed Design Procedure
        3. 9.2.5.3 Application Performance Plots
      6. 9.2.6 Solution With Minimum External Components
        1. 9.2.6.1 Design Requirements
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Layout

Layout Guidelines

Figure 67 shows a layout recommendation for the LP8860-Q1. Figure 67 is used to show the principles of good layout. This layout can be adapted to the actual application layout if and where possible. It is important that all boost components are close to each other and to the device; the high-current traces must be wide enough. VDD must be as noise-free as possible. Place a VDD bypass capacitor near the pin and ground it to a noise-free ground. A charge-pump capacitor and boost input and output capacitors must be connected to PGND. Here are some main points to help the PCB layout work:

  • Current loops need to be minimized:
    • For low frequency the minimal current loop can be achieved by placing the boost components as close to each other as possible. Input and output capacitor grounds need to be close to each other to minimize current loop size.
    • Minimal current loops for high frequencies can be achieved by making sure that the ground plane is intact under the current traces. High frequency return currents try to find route with minimum impedance, which is the route with minimum loop area, not necessarily the shortest path. Minimum loop area is formed when return current flows just under the positive current route in the ground plane, if the ground plane is intact under the route.
    • For high frequency the copper area capacitance must be taken into account. For example, the copper area for the drain of boost nMOSFET is a tradeoff between capacitance and components cooling capacity.
  • GND plane must be intact under the high current boost traces to provide shortest possible return path and smallest possible current loops for high frequencies.
  • Current loops when the boost switch is conducting and not conducting must be in the same direction in optimal case.
  • Inductors must be placed so that the current flows in the same direction as in the current loops. Rotating the inductor 180° changes current direction.
  • Use separate power and noise-free grounds. The power ground is used for boost converter return current and noise-free ground for more sensitive signals, like VDD bypass capacitor grounding as well as grounding the GND pins of the LP8860-Q1 itself.
  • Boost output feedback voltage to LEDs need to be taken out after the output capacitors, not straight from the diode cathode.
  • A small (for example, 39-pF) bypass capacitor must be placed close to the FB pin to suppress high frequency noise
  • VDD line must be separated from the high current supply path to the boost converter to prevent high frequency ripple affecting the chip behavior. A separate 1-µF bypass capacitor is used for the VDD pin, and it is grounded to noise-free ground.
  • Capacitor connected to charge pump output CPUMP must have 10-µF capacitance, grounded by shortest way to boost switch current sensing resistor. This capacitor must be as close as possible to CPUMP pin. This capacitor provides a greater peak current for gate driver and must be used even if the charge pump is disabled. If the charge pump is disabled, the VDD and CPUMP pins must be tied together.
  • Input and output capacitors need strong grounding (wide traces, many vias to PGND plane).
  • If two or more output capacitors are used, symmetrical layout must be used to get all capacitors working ideally.
  • Input/output ceramic capacitors have DC-bias effect. If the output capacitance is too low, it can cause boost to become unstable on some loads. DC bias characteristics need to be obtained from the component manufacturer; it is not taken into account on component tolerance. TI recommends X5R/X7R capacitors.

Layout Example

LP8860-Q1 layout_example_PCB_snvsa21.gif Figure 67. LP8860-Q1 Layout