Typical values are specified at VCC = 3.3 V and TA = 25°C (unless otherwise noted)
|VCC||Supply voltage applied at DVCC pin(1)(2)(3)||1.8(6)||3.6||V|
|VSS||Supply voltage applied at DVSS pin||0||V|
|TA||Operating free-air temperature||–40||85||°C|
|TJ||Operating junction temperature||–40||85||°C|
|CDVCC||Recommended capacitor at DVCC(5)||4.7||10||µF|
|fSYSTEM||Processor frequency (maximum MCLK frequency)(6)(4)||No FRAM wait states (NWAITSx = 0)||0||8||MHz|
|With FRAM wait states (NWAITSx = 1)(7)||0||16(8)|
|fACLK||Maximum ACLK frequency||40||kHz|
|fSMCLK||Maximum SMCLK frequency||16(8)||MHz|
(1) Supply voltage changes faster than 0.2 V/µs can trigger a BOR reset even within the recommended supply voltage range. Following the data sheet recommendation for capacitor CDVCC limits the slopes accordingly.
(2) Modules may have a different supply voltage range specification. See the specification of the respective module in this data sheet.
(3) TI recommends that power to the DVCC pin must not exceed the limits specified in Recommended Operating Conditions. Exceeding the specified limits can cause malfunction of the device including erroneous writes to RAM and FRAM.
(4) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
(5) A capacitor tolerance of ±20% or better is required. A low-ESR ceramic capacitor of 100 nF (minimum) should be placed as close as possible (within a few millimeters) to the respective pin pair.
The minimum supply voltage is defined by the SVS levels. See the SVS threshold parameters in Section 126.96.36.199
(7) Wait states only occur on actual FRAM accesses (that is, on FRAM cache misses). RAM and peripheral accesses are always executed without wait states.
(8) If clock sources such as HF crystals or the DCO with frequencies >16 MHz are used, the clock must be divided in the clock system to comply with this operating condition.