The clock system includes a 32-kHz crystal oscillator (XT1), an internal very low-power low-frequency oscillator (VLO), an integrated 32-kHz RC oscillator (REFO), an integrated internal digitally controlled oscillator (DCO) that may use frequency-locked loop (FLL) locking with internal or external 32-kHz reference clock, and on-chip asynchronous high-speed clock (MODCLK). The clock system is designed to target cost-effective designs with minimal external components. A fail-safe mechanism is designed for XT1. The clock system module offers the following clock signals.
All peripherals may have one or several clock sources depending on specific functionality. Table 9-6 shows the clock distribution used in this device.
|CLOCK SOURCE SELECT BITS||MCLK||SMCLK||ACLK||MODCLK||XT1CLK(1)||VLOCLK||EXTERNAL PIN|
|Frequency Range||DC to 16 MHz||DC to 16 MHz||DC to 40 kHz||5 MHz ±10%||DC to 40 kHz||10 kHz ±50%|
|TA0||TASSEL||10b||01b||00b (TA0CLK pin)|
|TA1||TASSEL||10b||01b||00b (TA1CLK pin)|
|eUSCI_A0||UCSSELx||10b or 11b||01b||00b (UCA0CLK pin)|
|eUSCI_B0||UCSSELx||10b or 11b||01b||00b (UCB0CLK pin)|
|ADC||ADCSSEL||10b or 11b||01b||00b|