SLOS224J July   1999  – February 2024 THS4031 , THS4032

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information: THS4031
    5. 5.5  Thermal Information: THS4032
    6. 5.6  Electrical Characteristics: THS4031, RL = 150 Ω
    7. 5.7  Electrical Characteristics: THS4031, RL = 1 kΩ
    8. 5.8  Electrical Characteristics: THS4032, RL = 150 Ω
    9. 5.9  Electrical Characteristics: THS4032, RL = 1 kΩ
    10. 5.10 Typical Characteristics: THS4031
    11. 5.11 Typical Characteristics: THS4032
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Offset Nulling
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Driving a Capacitive Load
      2. 7.1.2 Low-pass Filter Configurations
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Selection of Multiplexer
        2. 7.2.2.2 Signal Source
        3. 7.2.2.3 Driving Amplifier
        4. 7.2.2.4 Driving Amplifier Bandwidth Restriction
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 General PowerPAD™ Design Considerations
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.1.2 Low-pass Filter Configurations

When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required. Figure 7-2 shows how the simplest way to accomplish this limiting is to place an RC filter at the non-inverting pin of the amplifier.

GUID-20230927-SS0I-RSCW-PDDW-8XN16PSLVL5L-low.svg Figure 7-2 Single-pole Low-pass Filter
Equation 1. V O U T V I N = 1 + R F R G × 1 1 + s R 1 C 1

If more attenuation at higher frequencies is required, a multiple-pole filter is required. Figure 7-3 shows a common implementation of a second-order filter called a Sallen-Key filter. When designing this type of filter, chose an amplifier who bandwidth is approximately an order of magnitude larger than the desired filter bandwidth. See Active Low-pass Filter Design for more detailed active-filter design information.

Assuming R1 = R2 = R and C1 = C2 = C, use Equation 2 to set the bandwidth of the filter.

Equation 2. f3dB=12πRC

The Q-factor of a filter controls the amount of peaking of the small-signal frequency response and the settling time of the pulse response. Set Q to 0.707 to provide a Butterworth response with a maximally flat pass-band. Chose the ratio of RF and RG to obtain the desired Q value as shown in Equation 3.

Equation 3. RFRG=2-1Q
GUID-20230927-SS0I-B9P5-SD6T-LZZH4JTNRLDW-low.svg Figure 7-3 Two-pole Low-pass Sallen-Key Filter