SLOS224J July   1999  – February 2024 THS4031 , THS4032

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information: THS4031
    5. 5.5  Thermal Information: THS4032
    6. 5.6  Electrical Characteristics: THS4031, RL = 150 Ω
    7. 5.7  Electrical Characteristics: THS4031, RL = 1 kΩ
    8. 5.8  Electrical Characteristics: THS4032, RL = 150 Ω
    9. 5.9  Electrical Characteristics: THS4032, RL = 1 kΩ
    10. 5.10 Typical Characteristics: THS4031
    11. 5.11 Typical Characteristics: THS4032
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Offset Nulling
    4. 6.4 Device Functional Modes
  8. Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Driving a Capacitive Load
      2. 7.1.2 Low-pass Filter Configurations
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Selection of Multiplexer
        2. 7.2.2.2 Signal Source
        3. 7.2.2.3 Driving Amplifier
        4. 7.2.2.4 Driving Amplifier Bandwidth Restriction
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 General PowerPAD™ Design Considerations
      2. 7.4.2 Layout Example
  9. Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Typical Characteristics: THS4031

at TA = 25°C, VCC = ± 15 V, gain = +2 V/V, RL = 150 Ω, and RF = 300 Ω (unless otherwise noted)

GUID-20230929-SS0I-WDJT-VTM4-LGQ4ZGR8WNKB-low.svg
VCC = ±15 V, RL = 150 Ω, VOUT = 200 mVPP
Figure 5-1 Frequency Response vs Feedback Resistance
GUID-20230929-SS0I-MBPZ-QDJZ-4KTFJNXNCLT4-low.svg
VCC = ±5 V, RL = 150 Ω, VOUT = 200 mVPP
Figure 5-3 Frequency Response vs Feedback Resistance
GUID-20231003-SS0I-N871-HPLX-SFXVWW860ZV8-low.svg
Gain = +2 V/V, VOUT = 400 mVPP
Figure 5-5 Frequency Response vs Feedback Resistance
GUID-20231003-SS0I-MZJ8-BWNF-FFK4LMK9KDVB-low.svg
VCC = ±15 V
Figure 5-7 Large-Signal Frequency Response
GUID-20231003-SS0I-F4KQ-BH7V-JJK1DNJ1MKX2-low.svg
 
Figure 5-9 Closed-Loop Output Impedance
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Figure 5-11 Power-supply Rejection Ratio vs Frequency
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Figure 5-13 Input-referred Voltage Noise vs Frequency
GUID-20231003-SS0I-VBPD-R9JM-LDFRFKTHNXTD-low.svg
VCC = ±15 V, gain = +2 V/V, RL = 1 kΩ, VOUT = 2 VPP
Figure 5-15 Harmonic Distortion vs Frequency
GUID-20231003-SS0I-MLVV-8FDX-FSCFSL7XSN8H-low.svg
VCC = ±15 V, gain = +2 V/V, RL = 150 Ω, VOUT = 2 VPP
Figure 5-17 Harmonic Distortion vs Frequency
GUID-20231003-SS0I-4LVZ-CWQQ-9VKGGHRBBVBH-low.svg
VCC = ±15 V, gain = +5 V/V, RL = 1 kΩ, f = 1 MHz
Figure 5-19 Harmonic Distortion vs Peak‑to‑Peak Output Voltage
GUID-20231004-SS0I-BCRP-QBXW-DDLKSTPJS4CG-low.svg
Gain = +2 V/V
Figure 5-21 1-V Step Response
GUID-20231004-SS0I-BZ1M-SBF6-89SMSGMWKVMB-low.svg
Gain = +2 V/V
Figure 5-23 20-V Step Response
GUID-20231004-SS0I-NLR3-VXF8-7TSGMPKQNSH5-low.svg
μ = 0.209, σ = 0.0911
Figure 5-25 Voltage Offset Distribution
GUID-20231004-SS0I-8QT9-6RWQ-BLP2N6CD9WV5-low.svg
μ = 0.0179, σ = 0.0317
Figure 5-27 Input Offset Current vs Ambient Temperature
GUID-20231004-SS0I-4QZF-F5JW-HMPTWF9ZJBP0-low.svg
 
Figure 5-29 Maximum Output Voltage Swing vs Ambient Temperature
GUID-20231004-SS0I-2QVP-4H64-V0RXMWNNZSKQ-low.svg
 
Figure 5-31 Supply Current vs Ambient Temperature
GUID-20230929-SS0I-QT87-TL9J-1NVPFKW7TJ9K-low.svg
VCC = ±15 V, RL = 1 kΩ, VOUT = 200 mVPP
Figure 5-2 Frequency Response vs Feedback Resistance
GUID-20230929-SS0I-5DVR-Z3RS-MS3D7ZLGT4QH-low.svg
VCC = ±5 V, RL = 1 kΩ, VOUT = 200 mVPP
Figure 5-4 Frequency Response vs Feedback Resistance
GUID-20231003-SS0I-GMT5-94HP-FN6BBDXJJ3DP-low.svg
VCC = ±5 V, gain = +2 V/V, VOUT = 400 mVPP
Figure 5-6 Frequency Response vs Feedback Resistance
GUID-20231003-SS0I-VJXJ-RRW1-PDDQD48LZKXK-low.svg
VCC = ±5 V
Figure 5-8 Large-Signal Frequency Response
GUID-20231003-SS0I-X2T5-74HH-VNBW4VJ7T0FJ-low.svg
 
Figure 5-10 Open-loop Gain and Phase Response
GUID-20231003-SS0I-DXHT-GNJB-5WS66CD1BJFR-low.svg
 
Figure 5-12 Common-mode Rejection Ratio vs Frequency
GUID-20230828-SS0I-63PR-BDHJ-CVK6BS0QMTSK-low.svg
Figure 5-14 Input-referred Current Noise vs Frequency
GUID-20231003-SS0I-VRHF-PVQN-G4Z4TLZBSGT8-low.svg
VCC = ±5 V, gain = +2 V/V, RL = 1 kΩ, VOUT = 2 VPP
Figure 5-16 Harmonic Distortion vs Frequency
GUID-20231003-SS0I-L1XB-G27L-BB8MKJMCQFZ7-low.svg
VCC = ±5 V, gain = +2 V/V, RL = 150 Ω, VOUT = 2 VPP
Figure 5-18 Harmonic Distortion vs Frequency
GUID-20231003-SS0I-VDGR-91NZ-47MH4CWTT03J-low.svg
VCC = ±15 V, gain = +5 V/V, RL = 150 Ω, f = 1 MHz
Figure 5-20 Harmonic Distortion vs Peak‑to‑Peak Output Voltage
GUID-20231004-SS0I-8RHQ-3LD4-HQ8SCJZDN2BK-low.svg
VCC = ±5 V, gain =-1 V/V, RF = 430 Ω
Figure 5-22 4-V Step Response
GUID-20231004-SS0I-3HKP-FZSZ-ZCKHTRQVNSLR-low.svg
3 typical units
Figure 5-24 Input Offset Voltage vs Ambient Temperature
GUID-20231004-SS0I-ZBWW-4ZGM-R9CGNHJLTT8N-low.svg
3 typical units
Figure 5-26 Input Offset Current vs Ambient Temperature
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Figure 5-28 Offset Voltage vs Output Voltage
GUID-20231004-SS0I-HXR2-CQBB-GFJ3X5XCQBRP-low.svg
 
Figure 5-30 Output Swing vs Load Current