SLOS224J July   1999  – February 2024 THS4031 , THS4032

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information: THS4031
    5. 5.5  Thermal Information: THS4032
    6. 5.6  Electrical Characteristics: THS4031, RL = 150 Ω
    7. 5.7  Electrical Characteristics: THS4031, RL = 1 kΩ
    8. 5.8  Electrical Characteristics: THS4032, RL = 150 Ω
    9. 5.9  Electrical Characteristics: THS4032, RL = 1 kΩ
    10. 5.10 Typical Characteristics: THS4031
    11. 5.11 Typical Characteristics: THS4032
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Offset Nulling
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Driving a Capacitive Load
      2. 7.1.2 Low-pass Filter Configurations
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Selection of Multiplexer
        2. 7.2.2.2 Signal Source
        3. 7.2.2.3 Driving Amplifier
        4. 7.2.2.4 Driving Amplifier Bandwidth Restriction
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 General PowerPAD™ Design Considerations
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.6 Electrical Characteristics: THS4031, RL = 150 Ω

at TA = 25°C, VCC = ±15 V, and RL = 150 Ω (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DYNAMIC PERFORMANCE
BW Small-signal bandwidth (–3 dB)
Gain = –1 or 2
VCC = ±15 V
 		 100 MHz
VCC = ±5 V 90
Bandwidth for 0.1-dB flatness Gain = –1 or 2 VCC = ±15 V 9 MHz
VCC = ±5 V 9
SR Slew rate(1) Gain = –1
VCC = ±15 V, 20-V step
 		 100 V/μs

VCC = ±5 V, 5-V step

 80
tS Settling time to 0.1% Gain = –1 VCC = ±15 V, 5-V step 70 ns
VCC = ±5 V, 2.5-V step 55
Settling time to 0.01%
Gain = –1

 VCC = ±15 V, 5-V step 90 ns
VCC = ±5 V, 2.5-V step 80
THD+N Total harmonic distortion + noise Gain = 1, RL = 600 Ω, f = 1 kHz,
BW = 80 kHz		 VCC = ±15 V, VO=3 VRMS –137 dB
0.000014 %
VCC = ±5 V, VO=1 VRMS –130 dB
0.00003 %
Gain = 2, RL = 600 Ω, f = 1 kHz,
BW = 80 kHz		 VCC = ±15 V, VO=3 VRMS –133 dB
0.000022 %
VCC = ±5 V, VO=1 VRMS –124 dB
0.00006 %
IMD Intermodulation distortion G = 1, RL = 600 Ω, SMPTE/DIN two-tone, 4:1 (60 Hz and 7 kHz) VCC = ±15 V, VO=3 VRMS –130 dB
0.000032 %
VCC = ±5 V, VO=1 VRMS –126 dB
0.00005 %
G = 2, RL = 600 Ω, SMPTE/DIN two-tone, 4:1 (60 Hz and 7 kHz) VCC = ±15 V, VO=3 VRMS –126 dB
0.00005 %
VCC = ±5 V, VO=1 VRMS –120 dB
0.0001 %
NOISE/DISTORTION PERFORMANCE
THD Total Harmonic Distortion G =2, VCC = ±5 V or ±15 V, f = 1 MHz VO(pp) = 2 V –81 dBc
Vn Input voltage noise VCC = ±5 V or ±15 V, f > 10 kHz 1.2 nV/√Hz
In Input current noise VCC = ±5 V or ±15 V, f > 10 kHz 2.3 pA/√Hz
Differential gain error G = 2, 40 IRE modulation, NTSC and PAL, ±100 IRE ramp VCC = ±15 V 0.015%
VCC = ±5 V 0.02%
Differential phase error VCC = ±15 V 0.025 °
VCC = ±5 V 0.03
DC PERFORMANCE
Open loop gain VCC = ±15 V, VO = ±10 V TA = 25°C 93 100 dB
TA = full range 92 dB
VCC = ±5 V, VO = ±2.5 V TA = 25°C 90 98 dB
TA = full range 89 dB
VOS Input offset voltage VCC = ±5 V or ±15 V TA = 25°C 0.3 2 mV
TA = full range 3
Offset voltage drift VCC = ±5 V or ±15 V TA = full range 2 μV/°C
IIB Input bias current VCC = ±5 V or ±15 V TA = 25°C 9 20 μA
TA = full range 33
IOS Input offset current VCC = ±5 V or ±15 V TA = 25°C 30 250 nA
TA = full range 400
Input offset current VCC = ±5 V or ±15 V TA = full range 0.2 nA/°C
INPUT CHARACTERISTICS
VICR Common-mode input voltage range VCC = ±15 V ±13.5 ±14.3 V
VCC = ±5 V ±3.8 ±4.3
CMRR Common-mode rejection ratio VCC = ±15 V, VICR = ±12 V TA = 25°C 85 95 dB
TA = full range 80
VCC = ±5 V, VICR = ±2.5 V TA = 25°C 90 100
TA = full range 85
ri Input resistance 2 MΩ
Ci Input capacitance 1.5 pF
OUTPUT CHARACTERISTICS
VO Output voltage swing VCC = ±15 V RL = 250 Ω ±12 ±12.9 V
VCC = ±5 V ±3 ±3.5 V
IO Output current(2) RL = 10 Ω VCC = ±15 V 60 200 mA
VCC = ±5 V 50 160 mA
RO Output resistance Open loop 5 Ω
POWER SUPPLY
VCC Supply voltage operating range Dual supply ±4.5 ±16.5 V
Single supply 9 33
ICC Supply current (each amplifier) VCC = ±15 V TA = 25°C 7.5 10 mA
TA = full range 11
VCC = ±5 V TA = 25°C 6.5 9
TA = full range 10.5
PSRR Power-supply rejection ratio VCC = ±5 V or ±15 V TA = 25°C 85 95 dB
TA = full range 80
(1) Slew rate is measured from an output level range of 25% to 75%.
(2) Keep junction temperature less than the absolute maximum rating when the output is heavily loaded or shorted; see also Section 5.1