SLOS224J July   1999  – February 2024 THS4031 , THS4032

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information: THS4031
    5. 5.5  Thermal Information: THS4032
    6. 5.6  Electrical Characteristics: THS4031, RL = 150 Ω
    7. 5.7  Electrical Characteristics: THS4031, RL = 1 kΩ
    8. 5.8  Electrical Characteristics: THS4032, RL = 150 Ω
    9. 5.9  Electrical Characteristics: THS4032, RL = 1 kΩ
    10. 5.10 Typical Characteristics: THS4031
    11. 5.11 Typical Characteristics: THS4032
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Offset Nulling
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Driving a Capacitive Load
      2. 7.1.2 Low-pass Filter Configurations
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Selection of Multiplexer
        2. 7.2.2.2 Signal Source
        3. 7.2.2.3 Driving Amplifier
        4. 7.2.2.4 Driving Amplifier Bandwidth Restriction
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 General PowerPAD™ Design Considerations
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.1 Layout Guidelines

To achieve the levels of high-frequency performance of the THS403x, follow proper printed-circuit board (PCB), high-frequency design techniques. The following is a general set of guidelines. In addition, a THS403x evaluation board is available to use as a guide for layout or for evaluating the device performance.

  • Ground planes—make sure that the ground plane used on the board provides all components with a low-inductive ground connection. However, in the areas of the amplifier inputs and output, the ground plane can be removed to minimize stray capacitance.
  • Proper power-supply decoupling—use a 6.8-μF tantalum capacitor in parallel with a 0.1-μF ceramic capacitor on each supply pin. Sharing the tantalum capacitor among several amplifiers is possible depending on the application, but always use a 0.1-μF ceramic capacitor on the supply pin of every amplifier. In addition, place the 0.1-μF capacitor as close as possible to the supply pin. As this distance increases, the inductance in the connecting trace makes the capacitor less effective. Strive for distances of less than 0.1 inch (2.54 mm) between the device power pins and the ceramic capacitors.
  • Short trace runs or compact part placements—optimum high-frequency performance is achieved when stray series inductance is minimized. To minimize stray inductance, make the circuit layout as compact as possible, thereby minimizing the length of all trace runs. Pay particular attention to the inputs of the amplifier, keeping the trace lengths as short as possible. This layout helps to minimize stray capacitance at the input of the amplifier.
  • Sockets—TI does not recommend sockets for high-speed operational amplifiers. The additional lead inductance in the socket pins often leads to stability problems. Surface-mount packages soldered directly to the printed-circuit board is the best implementation.
  • Short trace runs and compact part placements—Improved high-frequency performance is achieved when stray series inductance is minimized. To reduce stray series inductance, the circuit layout must be made as compact as possible, thereby minimizing the length of all trace runs. Particular attention must be paid to the inverting input of the amplifier. The length must be kept as short as possible to minimize stray capacitance at the input of the amplifier.