SLIS187 June   2021 TLC6A598

ADVANCE INFORMATION  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Waveforms
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Serial-In Interface
      2. 8.3.2 Clear Registers
      3. 8.3.3 Output Channels
      4. 8.3.4 Register Clock
      5. 8.3.5 Cascade Through SER OUT
      6. 8.3.6 Output Control
      7. 8.3.7 Clamping Structure
      8. 8.3.8 Protection Functions
        1. 8.3.8.1 Over Current Protection
        2. 8.3.8.2 Output Detection
        3. 8.3.8.3 Serial Communication Error
        4. 8.3.8.4 Thermal Shutdown
      9. 8.3.9 Interface
        1. 8.3.9.1 Register Write
        2. 8.3.9.2 Register Read
        3. 8.3.9.3 Shift-Register Communication-Fault Detection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation With VCC < 3 V
      2. 8.4.2 Operation With 5.5 V ≤ VCC ≤ 7 V
    5. 8.5 Register Maps
      1. 8.5.1 Configuration Register(Offset=0h)[reset=0h]
      2. 8.5.2 Fault Readback Register(Offset=1h)[reset=0h]
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application 1
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
    3. 9.3 Typical Application 2
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedure
    4. 9.4 Typical Application 3
      1. 9.4.1 Design Requirements
      2. 9.4.2 Detailed Design Procedure
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Tape and Reel Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DW|24
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Configuration Register(Offset=0h)[reset=0h]

Configuration register is shown in Table 8-4and described in Table 8-5.

Table 8-4 Configuration Register
7 6 5 4 3 2 1 0
DRAIN7 DRAIN6 DRAIN5 DRAIN4 DRAIN3 DRAIN2 DRAIN1 DRAIN0
W-0h W-0h W-0h W-0h W-0h W-0h W-0h W-0h

Table 8-5 Configuration Register Field Descriptions
Bit Field Type Reset Description
7 DRAIN7 W 0h
  • Open-drain output bit for DRAIN7
  • HIGH=Output power switch enabled
  • LOW=Output power switch disabled
6 DRAIN6 W 0h
  • Open-drain output bit for DRAIN6
  • HIGH=Output power switch enabled
  • LOW=Output power switch disabled
5 DRAIN5 W 0h
  • Open-drain output bit for DRAIN5
  • HIGH=Output power switch enabled
  • LOW=Output power switch disabled
4 DRAIN4 W 0h
  • Open-drain output bit for DRAIN4
  • HIGH=Output power switch enabled
  • LOW=Output power switch disabled
3 DRAIN3 W 0h
  • Open-drain output bit for DRAIN3
  • HIGH=Output power switch enabled
  • LOW=Output power switch disabled
2 DRAIN2 W 0h
  • Open-drain output bit for DRAIN2
  • HIGH=Output power switch enabled
  • LOW=Output power switch disabled
1 DRAIN1 W 0h
  • Open-drain output bit for DRAIN1
  • HIGH=Output power switch enabled
  • LOW=Output power switch disabled
0 DRAIN0 W 0h
  • Open-drain output bit for DRAIN0
  • HIGH=Output power switch enabled
  • LOW=Output power switch disabled