SLIS187C June   2021  – March 2022 TLC6A598

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Waveforms
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Serial-In Interface
      2. 8.3.2 Clear Registers
      3. 8.3.3 Output Channels
      4. 8.3.4 Register Clock
      5. 8.3.5 Cascade Through SER OUT
      6. 8.3.6 Output Control
      7. 8.3.7 Clamping Structure
      8. 8.3.8 Protection Functions
        1. 8.3.8.1 Overcurrent Protection
        2. 8.3.8.2 Output Detection
        3. 8.3.8.3 Serial Communication Error
        4. 8.3.8.4 Thermal Shutdown
      9. 8.3.9 Interface
        1. 8.3.9.1 Register Write
        2. 8.3.9.2 Register Read
        3. 8.3.9.3 Shift-Register Communication-Fault Detection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation With VCC < 3 V
      2. 8.4.2 Operation With 5.5 V ≤ VCC ≤ 7 V
    5. 8.5 Register Maps
      1. 8.5.1 Configuration Register(Offset=0h)[reset=0h]
      2. 8.5.2 Fault Readback Register(Offset=1h)[reset=0h]
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application 1
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Typical Application 2
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedure
    4. 9.4 Typical Application 3
      1. 9.4.1 Design Requirements
      2. 9.4.2 Detailed Design Procedure
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V(BR)DSX DRAIN0 to DRAIN7 Drain-to-source
voltage		 ID = 1 mA 50 65 V
VSD Source-to-drain forward
voltage		 IF = 350 mA 0.9 1.1 V
VOH High-level output voltage IOH = –20 µA 4.9 4.99 V
SER OUT IOH = –4 mA 4.5 4.69
VOL Low-level output voltage IOH = 20 µA 0.02 V
SER OUT IOH = 4 mA 0.4
IIH High-level input current VI = 5 V 1 µA
IIL Low-level input current VI = 0 V –1 µA
IO(chop) Output current at which chopping
starts		 TA = 25°C 0.6 0.8 1.1 A
ICC Logic supply current VCC = 5 V, All outputs off, no clock signal 180 300 µA
VCC = 5 V, All outputs on, no clock signal 300 500
ICC(FRQ) Logic supply current at frequency fSRCK = 5 MHz, CL = 30 pF, all outputs on 360 600 µA
I(nom) Nominal current VDS(on) = 0.5 V, TC = 85°C 350 mA
IDSX Off-state drain current VDS = 40 V, TA = 25°C 1 µA
VDS = 40 V, TA = 125°C 1
Rds(on) Static drain-source on-state resistance VCC = 5 V, ID = 350 mA
Single channel on, TA = 25°C		 1 1.5 Ω
Rds(on) Static drain-source on-state resistance VCC = 3.3 V, ID=350 mA
Single channel on, TA = 25°C		 1.1 1.6 Ω
Rds(on) Static drain-source on-state resistance VCC = 5 V, ID = 150 mA
Single channel on, TA = 125°C		 1.5 2.2 Ω
Rds(on) Static drain-source on-state resistance VCC = 3.3 V, ID = 150 mA
Single channel on, TA = 125°C		 1.6 2.3 Ω
I(O_S_th) Load open and short detection threshold 8.5 15 25 mA
I(O_S_hys) Load open and short detection threshold hysteresis 5.7 mA
TSHUTDOWN Thermal shutdown threshold 150 175 200 °C
THYS Thermal shutdown hysteresis 18 °C