SBASA91 December 2020 TLV320ADC3120
The TLV320ADC3120 signal chain is comprised of very-low-noise, high-performance, and low-power analog blocks and highly flexible and programmable digital processing blocks. The high performance and flexibility combined with a compact package makes the TLV320ADC3120 optimized for a variety of end-equipments and applications that require multichannel audio capture. Figure 8-16 shows a conceptual block diagram that highlights the various building blocks used in the signal chain, and how the blocks interact in the signal chain.
The front-end PGA is very low noise, with a 120-dB dynamic range performance. Along with a low-noise and low-distortion, multibit, delta-sigma ADC, the front-end PGA enables the TLV320ADC3120 to record a far-field audio signal with very high fidelity, both in quiet and loud environments. Moreover, the ADC architecture has inherent antialias filtering with a high rejection of out-of-band frequency noise around multiple modulator frequency components. Therefore, the device prevents noise from aliasing into the audio band during ADC sampling. Further on in the signal chain, an integrated, high-performance multistage digital decimation filter sharply cuts off any out-of-band frequency noise with high stop-band attenuation.
The device also has an integrated programmable biquad filter that allows for custom low-pass, high-pass, or any other desired frequency shaping. Thus, the overall signal chain architecture removes the requirement to add external components for antialiasing low-pass filtering, and thus saves drastically on the external system component cost and board space. See the TLV320ADCx140 Integrated Analog Antialiasing Filter and Flexible Digital Filter application report for further details.
The signal chain also consists of various highly programmable digital processing blocks such as phase calibration, gain calibration, high-pass filter, digital summer or mixer, biquad filters, and volume control. The details on these processing blocks are discussed further in this section. The device also supports up to four digital PDM microphone recording channels when the analog record channels are not used. Channels 1 to 2 in the signal chain block diagram of Figure 8-16 are as described in this section, however, channels 3 to 4 only support the digital microphone recording option and do not support the digital summer or mixer option.
The desired input channels for recording can be enabled or disabled by using the IN_CH_EN (P0_R115) register, and the output channels for the audio serial interface can be enabled or disabled by using the ASI_OUT_EN (P0_R116) register. In general, the device supports simultaneous power-up and power-down of all active channels for simultaneous recording. However, based on the application needs, if some channels must be powered-up or powered-down dynamically when the other channel recording is on, then that use case is supported by setting the DYN_CH_PUPD_EN, P0_R117_D4 register bit to 1'b1.
The device supports an input signal bandwidth up to 80 kHz, which allows the high-frequency non-audio signal to be recorded by using a 176.4-kHz (or higher) sample rate.
For output sample rates of 48 kHz or lower, the device supports all features for 4-channel recording and various programmable processing blocks. However, for output sample rates higher than 48 kHz, there are limitations in the number of simultaneous channel recordings supported and the number of biquad filters and such. See the TLV320ADCx140 Sampling Rates and Programmable Processing Blocks Supported application report for further details.