SBASA91 December   2020 TLV320ADC3120

ADVANCE INFORMATION  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements: I2C Interface
    7. 7.7  Switching Characteristics: I2C Interface
    8. 7.8  Timing Requirements: TDM, I2S or LJ Interface
    9. 7.9  Switching Characteristics: TDM, I2S or LJ Interface
    10. 7.10 Timing Requirements: PDM Digital Microphone Interface
    11. 7.11 Switching Characteristics: PDM Digial Microphone Interface
    12. 7.12 Timing Diagrams
    13. 7.13 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Serial Interfaces
        1. 8.3.1.1 Control Serial Interfaces
        2. 8.3.1.2 Audio Serial Interfaces
          1. 8.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 8.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 8.3.1.2.3 Left-Justified (LJ) Interface
        3. 8.3.1.3 Using Multiple Devices With Shared Buses
      2. 8.3.2 Phase-Locked Loop (PLL) and Clock Generation
      3. 8.3.3 Input Channel Configurations
      4. 8.3.4 Reference Voltage
      5. 8.3.5 Programmable Microphone Bias
      6. 8.3.6 Signal-Chain Processing
        1. 8.3.6.1 Programmable Channel Gain and Digital Volume Control
        2. 8.3.6.2 Programmable Channel Gain Calibration
        3. 8.3.6.3 Programmable Channel Phase Calibration
        4. 8.3.6.4 Programmable Digital High-Pass Filter
        5. 8.3.6.5 Programmable Digital Biquad Filters
        6. 8.3.6.6 Programmable Channel Summer and Digital Mixer
        7. 8.3.6.7 Configurable Digital Decimation Filters
          1. 8.3.6.7.1 Linear Phase Filters
            1. 8.3.6.7.1.1 Sampling Rate: 8 kHz or 7.35 kHz
            2. 8.3.6.7.1.2 Sampling Rate: 16 kHz or 14.7 kHz
            3. 8.3.6.7.1.3 Sampling Rate: 24 kHz or 22.05 kHz
            4. 8.3.6.7.1.4 Sampling Rate: 32 kHz or 29.4 kHz
            5. 8.3.6.7.1.5 Sampling Rate: 48 kHz or 44.1 kHz
            6. 8.3.6.7.1.6 Sampling Rate: 96 kHz or 88.2 kHz
            7. 8.3.6.7.1.7 Sampling Rate: 192 kHz or 176.4 kHz
            8. 8.3.6.7.1.8 Sampling Rate: 384 kHz or 352.8 kHz
            9. 8.3.6.7.1.9 Sampling Rate 768 kHz or 705.6 kHz
          2. 8.3.6.7.2 Low-Latency Filters
            1. 8.3.6.7.2.1 Sampling Rate: 16 kHz or 14.7 kHz
            2. 8.3.6.7.2.2 Sampling Rate: 24 kHz or 22.05 kHz
            3. 8.3.6.7.2.3 Sampling Rate: 32 kHz or 29.4 kHz
            4. 8.3.6.7.2.4 Sampling Rate: 48 kHz or 44.1 kHz
            5. 8.3.6.7.2.5 Sampling Rate: 96 kHz or 88.2 kHz
            6. 8.3.6.7.2.6 Sampling Rate 192 kHz or 176.4 kHz
          3. 8.3.6.7.3 Ultra-Low Latency Filters
            1. 8.3.6.7.3.1 Sampling Rate: 16 kHz or 14.7 kHz
            2. 8.3.6.7.3.2 Sampling Rate: 24 kHz or 22.05 kHz
            3. 8.3.6.7.3.3 Sampling Rate: 32 kHz or 29.4 kHz
            4. 8.3.6.7.3.4 Sampling Rate: 48 kHz or 44.1 kHz
            5. 8.3.6.7.3.5 Sampling Rate: 96 kHz or 88.2 kHz
            6. 8.3.6.7.3.6 Sampling Rate 192 kHz or 176.4 kHz
            7. 8.3.6.7.3.7 Sampling Rate 384 kHz or 352.8 kHz
      7. 8.3.7 Automatic Gain Controller (AGC)
      8. 8.3.8 Digital PDM Microphone Record Channel
      9. 8.3.9 Interrupts, Status, and Digital I/O Pin Multiplexing
    4. 8.4 Device Functional Modes
      1. 8.4.1 Sleep Mode or Software Shutdown
      2. 8.4.2 Active Mode
      3. 8.4.3 Software Reset
    5. 8.5 Programming
      1. 8.5.1 Control Serial Interfaces
        1. 8.5.1.1 I2C Control Interface
          1. 8.5.1.1.1 General I2C Operation
          2. 8.5.1.1.2 I2C Single-Byte and Multiple-Byte Transfers
            1. 8.5.1.1.2.1 I2C Single-Byte Write
            2. 8.5.1.1.2.2 I2C Multiple-Byte Write
            3. 8.5.1.1.2.3 I2C Single-Byte Read
            4. 8.5.1.1.2.4 I2C Multiple-Byte Read
    6. 8.6 Register Maps
      1. 8.6.1 Device Configuration Registers
        1. 8.6.1.1 TLV320ADC3120 Access Codes
      2. 8.6.2 Page 0 Registers
      3. 8.6.3 Page 1 Registers
      4. 8.6.4 Programmable Coefficient Registers
        1. 8.6.4.1 Programmable Coefficient Registers: Page 2
        2. 8.6.4.2 Programmable Coefficient Registers: Page 3
        3. 8.6.4.3 Programmable Coefficient Registers: Page 4
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Two-Channel Analog Microphone Recording
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Example Device Register Configuration Script for EVM Setup
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Four-Channel Digital PDM Microphone Recording
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Example Device Register Configuration Script for EVM Setup
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Overview

The TLV320ADC3120 is a high-performance, low-power, flexible, 2-channel, audio analog-to-digital converter (ADC) with extensive feature integration. This device is intended for applications in voice-activated systems, professional microphones, audio conferencing, portable computing, communication, and entertainment applications. The high dynamic range of the device enables far-field audio recording with high fidelity. This device integrates a host of features that reduces cost, board space, and power consumption in space-constrained, battery-powered, consumer, home, and industrial applications.

The TLV320ADC3120 consists of the following blocks:

  • 2-channel, multibit, high-performance delta-sigma (ΔΣ) ADC
  • Configurable single-ended or differential audio inputs
  • Low-noise, programmable microphone bias output
  • Automatic gain controller (AGC)
  • Programmable decimation filters with linear-phase or low-latency filter
  • Programmable channel gain, volume control, biquad filters for each channel
  • Programmable phase and gain calibration with fine resolution for each channel
  • Programmable high-pass filter (HPF), and digital channel mixer
  • Pulse density modulation (PDM) microphone 4-channel interface with high-performance decimation filter
  • Integrated low-jitter phase-locked loop (PLL) supporting a wide range of system clocks
  • Integrated digital and analog voltage regulators to support single-supply operation

Communication to the TLV320ADC3120 to configure the control registers is supported using an I2C interface. The device supports a highly flexible audio serial interface [time-division multiplexing (TDM), I2S, or left-justified (LJ)] to transmit audio data seamlessly in the system across devices.

The device can support multiple devices by sharing the common I2C and TDM buses across devices. Moreover, the device includes a daisy-chain feature and a secondary audio serial output data pin. These features relax the shared TDM bus timing requirements and board design complexities when operating multiple devices for applications requiring high audio data bandwidth.

Table 8-1 lists the reference abbreviations used throughout this document to registers that control the device.

Table 8-1 Abbreviations for Register References
REFERENCE ABBREVIATION DESCRIPTION EXAMPLE
Page y, register z, bit k Py_Rz_Dk Single data bit. The value of a single bit in a register. Page 4, register 36, bit 0 = P4_R36_D0
Page y, register z, bits k-m Py_Rz_D[k:m] Range of data bits. A range of data bits (inclusive). Page 4, register 36, bits 3-0 = P4_R36_D[3:0]
Page y, register z Py_Rz One entire register. All eight bits in the register as a unit. Page 4, register 36 = P4_R36
Page y, registers z-n Py_Rz-Rn Range of registers. A range of registers in the same page. Page 4, registers 36, 37, 38 = P4_R36-R38