SNIS214E june   2021  – july 2023 TMP114

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C Interface Timing
    7. 7.7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 1.2 V Compatible Logic Inputs
      2. 8.3.2 Cyclic Redundancy Check (CRC)
      3. 8.3.3 Temperature Limits
      4. 8.3.4 Slew Rate Warning
      5. 8.3.5 NIST Traceability
    4. 8.4 Device Functional Modes
      1. 8.4.1 Continuous Conversion Mode
      2. 8.4.2 Shutdown Mode
        1. 8.4.2.1 One-Shot Temperature Conversions
    5. 8.5 Programming
      1. 8.5.1 Temperature Data Format
      2. 8.5.2 I2C and SMBus Interface
      3. 8.5.3 Device Address
      4. 8.5.4 Bus Transactions
        1. 8.5.4.1 Auto-Increment
        2. 8.5.4.2 Writes
          1. 8.5.4.2.1 CRC Enabled Writes
        3. 8.5.4.3 Reads
          1. 8.5.4.3.1 CRC Enabled Reads
        4. 8.5.4.4 General Call Reset Function
        5. 8.5.4.5 Time-Out Function
        6. 8.5.4.6 Coexist on I3C MixedBus
        7. 8.5.4.7 Cyclic Redundancy Check Implementation
    6. 8.6 Register Map
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Separate I2C Pullup and Supply Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Equal I2C Pullup and Supply Voltage Application
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedure
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • YMT|4
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6 I2C Interface Timing

minimum and maximum specifications are over –40°C to 125°C and VDD = 1.08 V to 1.98 V (unless otherwise noted)(1)
STANDARD MODE FAST MODE FAST MODE PLUS UNIT
Min Max Min Max Min Max
f(SCL) SCL operating frequency 1 100 1 400 1 1000 kHz
t(BUF) Bus-free time between STOP and START conditions 4.7 1.3 0.5 µs
t(SUSTA) Repeated START condition setup time 4.7 0.6 0.26 µs
t(HDSTA) Hold time after repeated START condition.
After this period, the first clock is generated.		 4.0 0.6 0.26 µs
t(SUSTO) STOP condition setup time 4.0 0.6 0.26 µs
t(HDDAT) Data hold time(2) 12 900 12 900 12 150 ns
t(SUDAT) Data setup time 250 100 50 ns
t(LOW) SCL clock low period 4.7 1.3 0.5 µs
t(HIGH) SCL clock high period 4.0 0.6 0.26 µs
t(VDAT) Data valid time (data response time)(3) 3.45 0.9 0.45 µs
tR SDA, SCL rise time 1000 20 300 120 ns
tF SDA, SCL fall time 300 20 x
(VDD / 5.5 V)		 300 20 x
(VDD / 5.5 V)		 120 ns
ttimeout Timeout (SCL = GND or SDA = GND) 23 36 23 36 23 37 ms
tLPF Glitch suppression filter 50 50 50 ns
(1) The controller and device have the same VDD value. Values are based on statistical analysis of samples tested during initial release.
(2) The maximum t(HDDAT) can be 0.9 µs for fast mode, and is less than the maximum t(VDAT) by a transition time.
(3) t(VDAT) = time for data signal from SCL LOW to SDA output (HIGH to LOW, depending on which is worse).