SNIS241 September   2025 TMP461-EP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Information
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Two-Wire Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Temperature Measurement Data
        1. 7.3.1.1 Decoding Temperature Data
      2. 7.3.2 Series Resistance Cancellation
      3. 7.3.3 Differential Input Capacitance
      4. 7.3.4 Filtering
      5. 7.3.5 Sensor Fault
      6. 7.3.6 ALERT and THERM Functions
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode (SD)
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
        1. 7.5.1.1 Bus Overview
        2. 7.5.1.2 Bus Definitions
        3. 7.5.1.3 Serial Bus Address
        4. 7.5.1.4 Read and Write Operations
        5. 7.5.1.5 Timeout Function
        6. 7.5.1.6 High-Speed Mode
      2. 7.5.2 General-Call Reset
  9. 8 Register Map
    1. 8.1 Register Information
      1. 8.1.1  Pointer Register
      2. 8.1.2  Local and Remote Temperature Registers
      3. 8.1.3  Status Register
      4. 8.1.4  Configuration Register
      5. 8.1.5  Conversion Rate Register
      6. 8.1.6  One-Shot Start Register
      7. 8.1.7  Channel Enable Register
      8. 8.1.8  Consecutive ALERT Register
      9. 8.1.9  η-Factor Correction Register
      10. 8.1.10 Remote Temperature Offset Register
      11. 8.1.11 Manufacturer Identification Register
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Related Documentation
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5.1.2 Bus Definitions

The TMP461-EP device is two-wire- and SMBus-compatible. Figure 7-6 and Figure 7-7 illustrate the timing for various operations on the TMP461-EP device. The bus definitions are as follows:

    Bus Idle:Both SDA and SCL lines remain high.
    Start Data Transfer:A change in the state of the SDA line (from high to low) when the SCL line is high defines a start condition. Each data transfer initiates with a start condition.
    Stop Data Transfer:A change in the state of the SDA line (from low to high) when the SCL line is high defines a stop condition. Each data transfer terminates with a repeated start or stop condition.
    Data Transfer:The number of data bytes transferred between a start and stop condition is not limited and is determined by the controller device. The receiver acknowledges the data transfer.
    Acknowledge:Each receiving device, when addressed, is obliged to generate an acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge clock pulse. Take setup and hold times into account. On a controller receive, data transfer termination can be signaled by the controller generating a not-acknowledge on the last byte that is transmitted by the target.
TMP461-EP Two-Wire Timing Diagram for Write Word Format
A. Target address 1001100 is shown.
Figure 7-6 Two-Wire Timing Diagram for Write Word Format
TMP461-EP Two-Wire Timing Diagram for Single-Byte Read Format
A. Target address 1001100 is shown.
B. The controller must leave SDA high to terminate a single-byte read operation.
Figure 7-7 Two-Wire Timing Diagram for Single-Byte Read Format