SLDS187A October 2018 – December 2019 TPS65216
PRODUCTION DATA.
CONFIG1 is shown in Figure 5-36 and described in Table 5-18.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRST | RESERVED | RESERVED | PGDLY | STRICT | UVLO | ||
R/W-0b | R/W-1b | R/W-0b | R/W-01b | R/W-1b | R/W-00b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | TRST | R/W, E2 | 0b |
Push-button reset time constant: 0b = 8 s 1b = 15 s |
6 | RESERVED | R/W | 1b |
|
5 | RESERVED | R/W | 0b |
|
4-3 | PGDLY | R/W, E2 | 01b |
Power-Good delay. Note: Power-good delay applies to rising-edge only (power-up), not falling edge (power-down or fault). 00b = 10 ms 01b = 20 ms 10b = 50 ms 11b = 150 ms |
2 | STRICT | R/W, E2 |
1b |
Supply Voltage Supervisor Sensitivity selection. See Section 4.5 for details. 0b = Power-good threshold (VOUT falling) has wider limits. Over-voltage is not monitored. 1b = Power-good threshold (VOUT falling) has tight limits. Over-voltage is monitored. |
1-0 | UVLO | R/W, E2 | 00b |
UVLO setting 00b = 2.75 V 01b = 2.95 V 10b = 3.25 V 11b = 3.35 V |