5.5.3.10 ENABLE1 Register (subaddress = 0x11) [reset = 0x00]
ENABLE1 is shown in Figure 5-34 and described in Table 5-16.
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Figure 5-34 ENABLE1 Register
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
RESERVED |
RESERVED |
RESERVED |
DC4_EN |
DC3_EN |
DC2_EN |
DC1_EN |
R-00b |
R/W-0b |
R/W-0b |
R/W-0b |
R/W-0b |
R/W-0b |
R/W-0b |
Table 5-16 ENABLE1 Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
7-6 |
RESERVED |
R |
00b |
|
5 |
RESERVED |
R/W |
0b |
|
4 |
RESERVED |
R/W |
0b |
|
3 |
DC4_EN |
R/W |
0b |
DCDC4 enable bit. Note: At power-up and down this bit is automatically updated by the internal power sequencer.
0b = Disabled
1b = Enabled
|
2 |
DC3_EN |
R/W |
0b |
DCDC3 enable bit. Note: At power-up and down this bit is automatically updated by the internal power sequencer.
0b = Disabled
1b = Enabled
|
1 |
DC2_EN |
R/W |
0b |
DCDC2 enable bit. Note: At power-up and down this bit is automatically updated by the internal power sequencer.
0b = Disabled
1b = Enabled
|
0 |
DC1_EN |
R/W |
0b |
DCDC1 enable bit. Note: At power-up and down this bit is automatically updated by the internal power sequencer.
0b = Disabled
1b = Enabled
|