SLDS187A October 2018 – December 2019 TPS65216
The internal LDO provides a regulated voltage to the internal digital core and analog circuitry. The internal LDO has a nominal output voltage of 2.5 V and can support up to 10 mA of external load.
When system power fails, the UVLO comparator triggers the power-down sequence. If system power drops below , the digital core is reset and all remaining power rails are shut down instantaneously and are pulled low to ground by their internal discharge circuitry (DCDC1-4 and LDO1).
The internal LDO reverse blocks to prevent the discharging of the output capacitor (CINT_LDO) on the INT_LDO pin. The remaining charge on the INT_LDO output capacitor provides a supply for the power rail discharge circuitry to ensure the outputs are discharged to ground even if the system supply has failed. The amount of hold-up time specified in Section 4.5 is a function of the output capacitor value (CINT_LDO) and the amount of external load on the INT_LDO pin, if any. The design allows for enough hold-up time to sufficiently discharge DCDC1-4, and LDO1 to ensure proper processor power-down sequencing.