SLDS187A October 2018 – December 2019 TPS65216
Power-good (PGOOD) is an open-drain output of the built-in voltage supervisor that monitors DCDC1, DCDC2, DCDC3, DCDC4, and LDO1. The output is Hi-Z when all enabled rails are in regulation and driven low when one or more rails encounter a fault which brings the output voltage outside the specified tolerance range. In a typical application PGOOD drives the reset signal of the SOC.
The supervisor has two modes of operation, controlled by the STRICT bit. With the STRICT bit set to 0, all enabled rails of the five regulators are monitored for undervoltage only with relaxed thresholds and deglitch times. With the STRCT bit set to 1, all enabled rails of the five regulators are monitored for undervoltage and overvoltage with tight limits and short deglitch times. Table 5-1 summarizes these details.
|PARAMETER||STRICT = 0b (TYP)||STRICT = 1b (TYP)|
|Undervoltage monitoring||Threshold (output falling)||90%|| 96.5% (DCDC1 and DCDC2)
95.5% (DCDC3, DCDC4, and LDO1)
|Deglitch (output falling)||1 ms||50 µs|
|Deglitch (output rising)||10 µs||10 µs|
|Overvoltage monitoring||Threshold (output falling)||N/A|| 103.5% (DCDC1 and DCDC2)
104.5% (DCDC3, DCDC4, and LDO1)
|Deglitch (output falling)||N/A||1 ms|
|Deglitch (output rising)||N/A||50 µs|
The following rules apply to the PGOOD output:
Figure 5-8 shows a typical power-up sequence and PGOOD timing.