JAJSIU8B June 2015 – April 2020 ADS131E08S
When the START pin is pulled high or when the START command is sent, the device ADCs begin converting the input signals and the data ready indicator, DRDY, is pulled high. The next DRDY falling edge indicates that data are ready. The settling time (tSETTLE) is the time required for the converter to output fully-settled data when the START signal is pulled high or the START command is issued. Figure 32 shows the timing diagram and Table 5 shows the settling time for different data rates. The settling time depends on fCLK and the decimation ratio (controlled by the DR[2:0] bits in the CONFIG1 register). Table 5 lists the settling time as a function of tCLK.