JAJSIU8B June 2015 – April 2020 ADS131E08S
The line voltage is stepped down to a voltage range within the measurable range of the ADC. The reference voltage determines the range in which the ADC can measure signals. The ADS131E08S has two integrated low-drift reference voltage options: 2.4 V and 4 V.
Equation 11 describes the transfer function for the voltage divider at the input in Figure 60. Using multiple series resistors, RDIV1, and multiple parallel resistors, RDIV2, allows for power and heat to be dissipated among several circuit elements and serves as protection against a potential short-circuit across a single resistor. The number of resistors trade off with nominal accuracy because each additional element introduces an additional source of tolerance.
The step-down resistor, RDiv2, dominates the measurement error produced by the resistor network. Using input PGAs on the ADS131E08S helps to mitigate this error source by allowing RDiv2 to be made smaller and then amplifying the signal to near full-scale using the ADS131E08S PGA.
For this design, RDiv1 is set to 200 kΩ and RDiv2 is set to 2.4 kΩ to provide proper signal attenuation at a sufficient power level across each resistor. The input saturates at values greater than ±750 V when using the ADS131E08S internal 2.4-V reference and a PGA gain of 2.
The ADS131E08S measures the line current by creating a voltage across the burden resistance (RBurden in Figure 60) in parallel with the secondary winding of a CT. As with the voltage measurement front-end, multiple resistors (RDiv1) that are used to step down a voltage share the duty of dissipating power. In this design, RBURDEN is set to 33 Ω. Used with a 1:500 turns ratio CT, the ADC input saturates with a line current over 25 A when the ADC is configured using the internal 2.4-V reference and a PGA gain of 2.
Diodes protect the ADS131E08S inputs from overvoltage and current. Diodes on each input shunt to either supply if the input voltage exceeds the safe range for the device. On current inputs, a diode shunts the inputs if current on the secondary winding of the CT threatens to damage the device.
The combination of RFilt, CCom, and CDif form the antialiasing filters for each of the inputs. The differential capacitor CDif improves the common-mode rejection of the system by sharing its tolerance between the positive and negative input. The antialiasing filter requirement is not strict because the nature of a ΔΣ converter (with oversampling and digital filter) attenuates a significant proportion of out-of-band noise. In addition, the input PGAs have intentionally low bandwidth to provide additional antialiasing. The component values used in this design are RFilt = 1 kΩ, CCom = 47 pF, and CDif = 0.015 μF. This first-order filter produces a relatively flat frequency response beyond 2 kHz, capable of measuring greater than 30 harmonics at a 50-Hz or 60-Hz fundamental frequency. The 3-dB cutoff frequency of the filter is 5.3 kHz for each input channel.
The ETU in a circuit breaker or protection relay can be powered from the line. In this case, fast power-up is required to allow the ADC to begin making measurements shortly after power is restored. The ADS131E08S is designed to fully power-up and collect data in less than 3 ms.
Each analog system block introduces errors from input to output. Protection CTs in the 5P accuracy class can introduce as much as ±1% current error from input to output. CTs in the 10P accuracy class can introduce as much as ±3% error. The burden resistor also introduces errors in the form of resistor tolerance and temperature drift. For the voltage input, error comes from the divider network in the form of resistor tolerance and temperature drift. Finally, the converter introduces errors in the form of offset error, gain error, and reference error. All of these specifications can drift over temperature.