JAJSIU8B June 2015 – April 2020 ADS131E08S
Chip select (CS) selects the ADS131E08S for SPI communication. CS must remain low for the duration of the serial communication. After the serial communication is finished, wait four or more tCLK cycles before taking CS high; see the Timing Requirements section. When CS is taken high, the serial interface is reset, SCLK and DIN are ignored (SCLK clears DRDY even when CS is high; see Figure 38 for more details), and DOUT enters a high-impedance state. DRDY asserts when data conversion is complete, regardless of whether CS is high or low.