JAJSL98B October   2020  – June 2021 LMG3522R030-Q1 , LMG3525R030-Q1


  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Device Comparison
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
  8. Parameter Measurement Information
    1. 8.1 Switching Parameters
      1. 8.1.1 Turn-On Delays
      2. 8.1.2 Turn-Off Delays
      3. 8.1.3 Drain Slew Rate
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Direct-Drive GaN Architecture
      2. 9.3.2 Drain-Source Voltage Capability
      3. 9.3.3 Internal Buck-Boost DC-DC Converter
      4. 9.3.4 VDD Bias Supply
      5. 9.3.5 Auxiliary LDO
      6. 9.3.6 Fault Detection
        1. Overcurrent Protection and Short-Circuit Protection
        2. Overtemperature Shutdown
        3. UVLO Protection
        4. Fault Reporting
      7. 9.3.7 Drive Strength Adjustment
      8. 9.3.8 Temperature-Sensing Output
      9. 9.3.9 Sync-FET Mode Operation
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. Slew Rate Selection
          1. Start-Up and Slew Rate With Bootstrap High-Side Supply
        2. Signal Level-Shifting
        3. Buck-Boost Converter Design
    3. 10.3 Do's and Don'ts
  11. 11Power Supply Recommendations
    1. 11.1 Using an Isolated Power Supply
    2. 11.2 Using a Bootstrap Diode
      1. 11.2.1 Diode Selection
      2. 11.2.2 Managing the Bootstrap Voltage
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Power Loop Inductance
      2. 12.1.2 Signal Ground Connection
      3. 12.1.3 Bypass Capacitors
      4. 12.1.4 Switch-Node Capacitance
      5. 12.1.5 Signal Integrity
      6. 12.1.6 High-Voltage Spacing
      7. 12.1.7 Thermal Recommendations
    2. 12.2 Layout Examples
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Export Control Notice
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information
    1. 14.1 Tape and Reel Information



  • RQS|52

Drain-Source Voltage Capability

Due to the silicon FET’s long reign as the dominant power-switch technology, many designers are unaware that the headline drain-source voltage cannot be used as an equivalent point to compare devices across technologies. The headline drain-source voltage of a silicon FET is set by the avalanche breakdown voltage. The headline drain-source voltage of a GaN FET is set by the long term reliability with respect to data sheet specifications.

Exceeding the headline drain-source voltage of a silicon FET can lead to immediate and permanent damage. Meanwhile, the breakdown voltage of a GaN FET is much higher than the headline drain-source voltage. For example, the breakdown voltage of the LMG352xR030-Q1 is more than 800 V.

A silicon FET is usually the weakest link in a power application during an input voltage surge. Surge protection circuits must be carefully designed to ensure the silicon FET avalanche capability is not exceeded because it is not feasible to clamp the surge below the silicon FET breakdown voltage. Meanwhile, it is easy to clamp the surge voltage below a GaN FET breakdown voltage. In fact, a GaN FET can continue switching during the surge event which means output power is safe from interruption.

The LMG352xR030-Q1 drain-source capability is explained with the assistance of Figure 9-2. The figure shows the drain-source voltage versus time for a GaN FET for a single switch cycle in a switching application. No claim is made about the switching frequency or duty cycle.

GUID-20210323-CA0I-V3JW-WD20-S9THKBTW2FMH-low.gif Figure 9-2 Drain-Source Voltage Switching Cycle

The waveform starts before t0 with the FET in the on state. At t0 the GaN FET turns off and parasitic elements cause the drain-source voltage to ring at high frequency. The peak ring voltage is designated VDS(tr). The high frequency ringing has damped out by t1. Between t1 and t2 the FET drain-source voltage is set by the characteristic response of the switching application. The characteristic is shown as a flat line, but other responses are possible. The voltage between t1 and t2 is designated VDS(off). At t2 the GaN FET is turned on at a non-zero drain-source voltage. The drain-source voltage at t2 is designated VDS(switching). Unique VDS(tr), VDS(off) and VDS(switching) parameters are shown because each can contribute to stress over the lifetime of the GaN FET.

The LMG352xR030-Q1 drain-source surge voltage capability is seen with the absolute maximum ratings VDS(tr) and VDS(surge) in Absolute Maximum Ratings where VDS(surge) is the same as VDS(off) and VDS(switching) in Figure 9-2. More information about the surge capability of TI GaN FETs is found in A New Approach to Validate GaN FET Reliability to Power-line Surges Under Use-conditions.