The LMG352xR030-Q1 uses a series Si FET to ensure the power IC stays off when VDD bias power is not applied. When the VDD bias power is off, the series Si FET is interconnected with the GaN device in a cascode mode, which is shown in Figure 9-1. The gate of the GaN device is held within a volt of the series Si FET's source. When a high voltage is applied on the module and the silicon FET blocks the drain voltage, the VGS of the GaN device decreases until the GaN device passes the threshold voltage. Then, the GaN device is turned off and blocks the remaining major part of drain voltage. There is an internal clamp to make sure that the VDD does not exceed its maximum rating. This avoids the avalanche of the series Si FET when there is no bias power.
When LMG352xR030-Q1 is powered up with VDD bias power, the internal buck-boost converter generates a negative voltage (VVNEG) that is sufficient to directly turn off the GaN device. In this case, the series Si FET is held on and the GaN device is gated directly with the negative voltage. During operation, this removes the switching loss of the series Si FET.