JAJSL98B October   2020  – June 2021 LMG3522R030-Q1 , LMG3525R030-Q1

ADVANCE INFORMATION  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Device Comparison
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
  8. Parameter Measurement Information
    1. 8.1 Switching Parameters
      1. 8.1.1 Turn-On Delays
      2. 8.1.2 Turn-Off Delays
      3. 8.1.3 Drain Slew Rate
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Direct-Drive GaN Architecture
      2. 9.3.2 Drain-Source Voltage Capability
      3. 9.3.3 Internal Buck-Boost DC-DC Converter
      4. 9.3.4 VDD Bias Supply
      5. 9.3.5 Auxiliary LDO
      6. 9.3.6 Fault Detection
        1. 9.3.6.1 Overcurrent Protection and Short-Circuit Protection
        2. 9.3.6.2 Overtemperature Shutdown
        3. 9.3.6.3 UVLO Protection
        4. 9.3.6.4 Fault Reporting
      7. 9.3.7 Drive Strength Adjustment
      8. 9.3.8 Temperature-Sensing Output
      9. 9.3.9 Sync-FET Mode Operation
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Slew Rate Selection
          1. 10.2.2.1.1 Start-Up and Slew Rate With Bootstrap High-Side Supply
        2. 10.2.2.2 Signal Level-Shifting
        3. 10.2.2.3 Buck-Boost Converter Design
    3. 10.3 Do's and Don'ts
  11. 11Power Supply Recommendations
    1. 11.1 Using an Isolated Power Supply
    2. 11.2 Using a Bootstrap Diode
      1. 11.2.1 Diode Selection
      2. 11.2.2 Managing the Bootstrap Voltage
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Power Loop Inductance
      2. 12.1.2 Signal Ground Connection
      3. 12.1.3 Bypass Capacitors
      4. 12.1.4 Switch-Node Capacitance
      5. 12.1.5 Signal Integrity
      6. 12.1.6 High-Voltage Spacing
      7. 12.1.7 Thermal Recommendations
    2. 12.2 Layout Examples
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Export Control Notice
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information
    1. 14.1 Tape and Reel Information

パッケージ・オプション

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メカニカル・データ(パッケージ|ピン)
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発注情報

Electrical Characteristics

Unless otherwise noted: voltage, resistance, capacitance, and inductance are respect to SOURCE connected with reference ground; –40 ℃ ≤ TJ ≤ 125 ℃; 9 V ≤ VVDD ≤ 18 V; VIN = 5 V; RDRV connected to LDO5V;  LBBSW = 4.7 µH
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
GAN POWER TRANSISTOR
RDS(on) Total on-state resistance TJ = 25°C 30 39
TJ = 125°C 56 73
VSD Third-quadrant mode source-drain voltage IN = 0 V, ISD = 0.1 A 5 V
IN = 0 V, ISD = 20 A 7 V
IDSS Drain leakage current VDS = 650 V, TJ = 25°C 1 5 uA
VDS = 650 V, TJ = 125°C 10 uA
COSS GaN output capacitance IN = 0 V, VDS = 400 V 218 pF
CO(er) Energy related effective output capacitance IN = 0 V, VDS = 0-400 V 276 pF
CO(tr) Time related effective output capacitance 438 pF
EOSS Energy in output capacitance. 21 22 24.4 uJ
QOSS Output charge 175 nC
QRR Reverse recovery charge(1) 0 nC
SUPPLY CURRENTS
IQ VDD quiescent current (LMG3522) VVDD = 12 V, VIN = 0 V or 5V, RDRV shorted to LDO5V 700 1200 uA
IQ VDD quiescent current (LMG3525) VVDD = 12 V, VIN = 0 V or 5V, RDRV shorted to LDO5V 780 1300 uA
I(op) VDD operating current VVDD = 12 V, fIN  = 140 kHz, soft-switching 16 19 mA
BUCK BOOST CONVERTER
VNEG average output voltage VNEG sinking 50 mA -14.6 -14 -13.4 V
BBSW switching frequency VVDD = 9 V, VNEG sinking 150 mA, LBBSW = 4.7 µH,
LBBSW peak current = 1 A
900 kHz
Peak BBSW sourcing current at low peak current mode setting VNEG sinking 25 mA, LDCDC = 4.7 µH, CVNEG = 2.2 µF 0.3 0.4 0.5 A
Peak BBSW sourcing current at high peak current mode setting VNEG sinking 100 mA, LBBSW = 4.7 µH, CVNEG = 2.2 µF 0.8 1 1.2 A
High peak current mode setting enable – BBSW positive-going input threshold frequency 280 400 515 kHz
5 V LDO
Output voltage LDO5V sourcing 25 mA 4.75 5 5.25 V
Short-circuit current 25 50 100 mA
DIGITAL INPUT PINS
VIN,IT+ Positive-going input threshold voltage 1.7 2.45 V
VIN,IT- Negative-going input threshold voltage 0.7 1.3 V
Input threshold hysteresis 0.8 0.83 1.5 V
Input pull-down resistance V= 2 V 100 150 200
FAULT PINS
Low-level output voltage Output sinking 8 mA 0.16 0.4 V
High-level output voltage Output sourcing 8 mA, Measured as
VLDO5V – VO
0.2 0.4 V
UNDER VOLTAGE LOCKOUT
VVDD,IT+(UVLO) VDD UVLO – positive-going input threshold voltage 6.6 7 7.6 V
VVDD,IT-(UVLO) VDD UVLO – negative-going input threshold voltage 6.1 6.5 6.8 V
VDD UVLO – Input threshold voltage hysteresis 680 mV
VVNEG,IT-(UVLO) VNEG UVLO – negative-going input threshold voltage -13.6 -13.0 -12.4 V
VVNEG,IT+(UVLO) VNEG UVLO – positive-going input threshold voltage -13.2 -12.75 -12.2 V
GATE DRIVER
Turnon drain slew rate From VDS < 320 V to VDS < 80 V, RDRV connected to RRDRV = 200 kΩ, TJ = 25 ℃, VBUS = 400 V, LHB current = 10 A, see Figure 8-1 20 V/ns
From VDS < 320 V to VDS < 80 V, RDRV directly connected to LDO5V, TJ = 25 ℃, VBUS = 400 V, LHB current = 10 A, see Figure 8-1 100 V/ns
From VDS < 320 V to VDS < 80 V, RDRV connected to ground, TJ = 25 ℃, VBUS = 400 V, LHB current = 10 A, see Figure 8-1   150 V/ns
Slew rate variation From VDS < 320 V to VDS < 80 V, RDRV directly connected to LDO5V, TJ = 25 ℃, VBUS = 400 V, LHB current = 10 A, see Figure 8-1 25 %
FIN(max) Maximum GaN FET switching frequency. VNEG rising to > –13.25 V, soft-switched, maximum switching frequency derated for VVDD < 9 V 2.2 MHz
FAULTS
IIT(OC) DRAIN overcurrent fault – input threshold current 70 A
ITRIP,SC DRAIN short-circuit fault – input threshold current 95 A
di/dt threshold between overcurrent and short-circuit faults 150 A/µs
Short-circuit current to overcurrent fault trip difference 25 A
GaN temperature fault – postive-going input threshold temperature 165 °C
Driver temperature fault – positive-going input threshold temperature
 
185 °C
GaN / Driver Temperature fault – input threshold temperature hysteresis 20 °C
PWM TEMPERATURE OUTPUT
Digital Temperature Report Output Frequency 6 11 18 kHz
Output PWM Duty Cycle GaN TJ = 150 ℃ 80 %
Output PWM Duty Cycle GaN TJ = 125 ℃ 65 %
Output PWM Duty Cycle GaN TJ = 85 ℃ 40 %
Output PWM Duty Cycle GaN TJ = 25 ℃ 3 %
THIRD QUADRANT TURN ON (LMG3525x, 26x)
VIT(3rd) Drain-source third-quadrant detection – input threshold voltage VIN = 0 V -0.15 0 0.15 V
IIT(ZC) Drain zero-current detection – input threshold current VIN = 0 V -0.2 0 0.2 A
Excluding Qoss