SLVUCF3 March   2022 DRA829V , LP8764-Q1 , TDA4VM , TPS6594-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Device Versions
  4. 3Processor Connections
    1. 3.1 Power Mapping
    2. 3.2 Control Mapping
  5. 4Supporting Functional Safety Systems
    1. 4.1 Achieving ASIL-B System Requirements
    2. 4.2 Achieving up to ASIL-D System Requirements
  6. 5Static NVM Settings
    1. 5.1  Application-Based Configuration Settings
    2. 5.2  Device Identification Settings
    3. 5.3  BUCK Settings
    4. 5.4  LDO Settings
    5. 5.5  VCCA Settings
    6. 5.6  GPIO Settings
    7. 5.7  Finite State Machine (FSM) Settings
    8. 5.8  Interrupt Settings
    9. 5.9  POWERGOOD Settings
    10. 5.10 Miscellaneous Settings
    11. 5.11 Interface Settings
    12. 5.12 Multi-Device Settings
    13. 5.13 Watchdog Settings
  7. 6Pre-Configurable Finite State Machine (PFSM) Settings
    1. 6.1 Configured States
    2. 6.2 PFSM Triggers
    3. 6.3 Power Sequences
      1. 6.3.1 TO_SAFE_SEVERE and TO_SAFE
      2. 6.3.2 TO_SAFE_ORDERLY and TO_STANDBY
      3. 6.3.3 ACTIVE_TO_WARM
      4. 6.3.4 ESM_SOC_ERROR
      5. 6.3.5 TO_ACTIVE
      6. 6.3.6 TO_RETENTION
  8. 7Application Examples
    1. 7.1 Initialization
    2. 7.2 Moving Between States; ACTIVE and RETENTION
      1. 7.2.1 ACTIVE
      2. 7.2.2 RETENTION
    3. 7.3 Entering and Exiting Standby
    4. 7.4 Entering and Existing LP_STANDBY
    5. 7.5 Runtime Customization
  9. 8References

2 Device Versions

There are different orderable part numbers (OPNs) of the TPS6594-Q1 and LP8764-Q1 devices available with NVM settings to support different end product use cases and processor types. The PDN-1A use case supports combined MCU and SOC rails for extended MCU operation where the PDN-0C and PDN-0B supports independent MCU and SOC rails for a dedicated MCU Safety Island. Since both PDN-1A and PDN-0C include the TPS65941213 device, in PDN-1A an additional step is required by the processor to reconfigure the PMICs so that all SOC power rail errors are mapped to the MCU Power error trigger in the PFSM. The context for this mapping is described throughout the document and specific instructions are provided in Section 7.1.

The NVM settings can be identified by both NVM_ID and NVM_REV registers. Each PMIC device is distinguished by the part number, NVM_ID, and NVM_REV values listed in Table 2-1.

Table 2-1 TPS6594-Q1 and LP8764-Q1 Orderable Part Numbers for PDN System
PDN USE CASEPDN Orderable Part NumberTI_NVM_ID (TI_NVM_REV)Orderable Part NumberTI_NVM_ID (TI_NVM_REV)Error Signal Monitoring
  • Up to 10.5 A(1) on the Primary PMIC 3-phase CPU rail
  • Up to 20 A(1) on the Secondary PMIC 4-phase CORE rail
  • Up to 3.4 A(1) on the SDRAM, with support for LPDDR4
  • Supports Processor 2 GHz maximum clock with high-speed SERDES operations
  • Supports 8 Gb of LPDDR4 SDRAM with 4266MTs data rate
  • Supports Functional Safety up to ASIL-D level
  • Supports DDR Retention low power mode
  • Supports I/O level of 3.3 V or 1.8 V
  • Supports optional end product features:
    • Compliant high-speed SD Card memory
    • Compliant USB 2.0 Interface
    • On-board Efuse programming of high security processors(3)
 1A(2) TPS65941213 RWERQ1 0x13 (0x04) LP876411B4RQKRQ1 0xB4 (0x00) Dedicated MCU and SOC
  • Up to 10.5 A(1) on the Primary PMIC 3-phase CPU rail
  • Up to 14 A(1) on the Secondary PMIC 4-phase CORE rail
  • Up to 3.4 A(1) on the SDRAM, with support for LPDDR4
  • Supports Processor 2 GHz maximum clock with high-speed SERDES operations
  • Supports 8GB of LPDDR4 SDRAM with 4266MTs data rate
  • Supports Functional Safety up to ASIL-D level with MCU Safety Island
  • Supports MCU-only and DDR Retention low power modes
  • Supports I/O level of 3.3 V or 1.8 V
  • Supports optional end product features:
    • Compliant high-speed SD Card memory
    • Compliant USB 2.0 Interface
    • On-board Efuse programming of high security processors
0C(2)TPS65941213 RWERQ10x13 (0x04)TPS65941111 RWERQ10x11 (0x03)Dedicated MCU and SOC
0BTPS65941212 RWERQ10x12 (0x03)TPS65941111 RWERQ10x11 (0x03)Combined MCU and SOC
(1) TI recommends having 15% margin between the maximum expected load current and the maximum current allowed per each PMIC output rail.
(2) PDN-0C and PDN-1A are recommended for all new designs.
(3) Efuse functionality is not part of the NVM in PDN-1A. This feature can be enabled during runtime.