SLVUCF3 March   2022 DRA829V , LP8764-Q1 , TDA4VM , TPS6594-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Device Versions
  4. 3Processor Connections
    1. 3.1 Power Mapping
    2. 3.2 Control Mapping
  5. 4Supporting Functional Safety Systems
    1. 4.1 Achieving ASIL-B System Requirements
    2. 4.2 Achieving up to ASIL-D System Requirements
  6. 5Static NVM Settings
    1. 5.1  Application-Based Configuration Settings
    2. 5.2  Device Identification Settings
    3. 5.3  BUCK Settings
    4. 5.4  LDO Settings
    5. 5.5  VCCA Settings
    6. 5.6  GPIO Settings
    7. 5.7  Finite State Machine (FSM) Settings
    8. 5.8  Interrupt Settings
    9. 5.9  POWERGOOD Settings
    10. 5.10 Miscellaneous Settings
    11. 5.11 Interface Settings
    12. 5.12 Multi-Device Settings
    13. 5.13 Watchdog Settings
  7. 6Pre-Configurable Finite State Machine (PFSM) Settings
    1. 6.1 Configured States
    2. 6.2 PFSM Triggers
    3. 6.3 Power Sequences
      1. 6.3.1 TO_SAFE_SEVERE and TO_SAFE
      2. 6.3.2 TO_SAFE_ORDERLY and TO_STANDBY
      3. 6.3.3 ACTIVE_TO_WARM
      4. 6.3.4 ESM_SOC_ERROR
      5. 6.3.5 TO_ACTIVE
      6. 6.3.6 TO_RETENTION
  8. 7Application Examples
    1. 7.1 Initialization
    2. 7.2 Moving Between States; ACTIVE and RETENTION
      1. 7.2.1 ACTIVE
      2. 7.2.2 RETENTION
    3. 7.3 Entering and Exiting Standby
    4. 7.4 Entering and Existing LP_STANDBY
    5. 7.5 Runtime Customization
  9. 8References

3.1 Power Mapping

Figure 3-1 shows the power mapping between the PMIC power resources and processor voltage domains required . In this configuration, both PMICs use a 3.3 V input voltage. For Functional Safety applications, there is a protection FET before VCCA that connects to the OVPGDRV pin of the primary PMIC, allowing voltage monitoring of the input supply to the PMICs.

For SD card dual-voltage I/O support (3.3 V and 1.8 V), a discrete LDO, TLV7103318-Q1, is included. The enable pin of this LDO is connected to GPIO10 of the LP876411B4-Q1 PMIC.

This PDN uses five discrete power components with two being required and three optional depending upon end product features. The TPS22965-Q1 Load Switch connects VCCA_3V3 power rail to supply OV protected 3.3 V to processor I/O domains. The TPS62813-Q1 Buck Converter supplies the LPDDR4 SDRAM component with required 1.1V supply. The three optional discrete power components are the LDOs. The TLV3333-Q1 provides 3.3V for the USB. TLV7103318-Q1 provides the selectable dual voltage for the SD card. The third LDO is an TLV73318-Q1 that can be used if an end product uses a high security processor type and desires the capability to program Efuse values on-board. If this feature is not desired, then this LDO can be omitted and processor pins terminated per data manual recommendations.

Note: The PMIC voltage monitor on FB_B3 of the TPS65941213 must be connected to 3.3 V. The VMON_ABIST_EN=1 for both the primary and secondary PMICs. If 3.3 V is not connected to FB_B3 when the monitor is enabled then the self-test fails, the BIST_FAIL_INT interrupt is set, and the device goes to the hardware SAFE RECOVERY state, see Figure 6-1, and main processor voltages are disabled.

Figure 3-1 shows that only VDD1_LPDDR_1V8 and VDD_DDR_1V1 are associated with the retention low power mode and that the MCU Only low power mode is not available. While the MCU Only modes is not supported, the TPS65941213-Q1 regulators are grouped separately between MCU and SOC power rail groups based upon PDN-0C, and described in Section 5.7. By default, any SOC power failure results in all SOC regulators being turned off (this includes VDD_IO_3V3) while MCU rail group regulators remain on. The sequence places the system in a non-functional state. In order to minimize the probability of this occurring it is recommended to map all SOC power errors to the MCU power error trigger. The I2C commands required to perform the mapping are provided in Section 7.1.

The FB_B3 of the TPS65941213-Q1 is part of the MCU_RAIL_GRP, as described here Section 5.7. By connecting FB_B3 of the TPS65941213-Q1 to the VDD_IO_3V3 rail, the PMIC automatically transitions to the safe state in the event of an SOC power error and the mapping of the SOC power error to the MCU power error trigger is not required.

Figure 3-1 Power Connections

  • * VDD_CPU_AVS, boot voltage of 0.8 V then software sets device specific AVS; 0.68 V – 0.72 V.
  • ** When FB_B3 is connected to the VCCA_3V3, the SOC_RAIL_TRIG must be set to MCU Power error for each PMIC.

Table 3-1 identifies which power resources are required to support different system features. In the Active SoC column, there is an additional option for including or excluding the VPP_x(EFUSE) rail. TLV7103318-Q1 and TLV73333-Q1, which support optional SD CARD and USB Interface features respectively, are enabled by GPIO10 of the LP876411B4-Q1 device. These options are illustrated as part of the power on sequence as shown in Figure 6-6.

Table 3-1 PDN Power Mapping and System Features
Power Mapping System Features(1)
Device Power Resource Power Rails Processor and Memory Domains Active SoC DDR Retention SD Card USB Interface
TPS65941213-Q1 BUCK123 VDD_CPU_AVS VDD_CPU R
FB_B3 VCCA_3V3(2) NA R
BUCK4 VDD_MCU_0V85 VDDAR_MCU, VDD_MCU R
VDDAR_CORE, VDDAR_CPU
BUCK5 VDD_PHY_1V8 VDDA_1P8_PHYs R
UFS: VCCQ
LDO1 VDD1_DDR_1V8 Mem: VDD1 R R(3)
LDO2 VDD_IO_1V8 VDDSHV1_MCU (1.8 V) R
VDDS_MMC0
Octal SPI Flash: VCC
eMMC: VCCQ
LDO3 VDA_DLL_0V8 VDDA_0P8_PLLs/DLLs R
LDO4 VDA_MCU_1V8 VDDA_x R
1.8V Analog CLK/PLLs
LP876511B4-Q1 BUCK1234 VDD_CORE_0V8 VDD_CORE, VDDA_0P8_PHYs R
TPS22965-Q1 Load Switch VDD_IO_3V3 VDDSHV0_MCU,VDDSHV2_MCU R
VDDSHV0-4,VDDSHV6 (3.3 V)
eMMC, VCC
UFS, VCC
TPS62813-Q1 BUCK VDD_DDR_1V1 VDDS_DDR_BIAS, VDDS_DDR_IO R R(4)
Mem: VDD2
TLV3333-Q1 LDO VDD_USB_3V3 VDDA_3p3_USB O R
TLV7103318-Q1 LDO VDD_SD_DV VDDSHV5 (3.3V or 1.8V) O R
TLV73318P-Q1 LDO VPP_EFUSE_1V8 VPP_x(EFUSE) O
(1) 'R' is required and 'O' is optional.
(2) Connecting FB_B3 to the VDD_IO_3V3_LS which supplies VDD_IO_3V3 is an alternative connection.
(3) LDO1 of the TPS65941213-Q1 remains on when TRIGGER_I2C_7, in FSM_I2C_TRIGGERS Register, is set.
(4) The TPS62813-Q1 is controlled by the LP876411B4-Q1 GPIO1 and remains active while TRIGGER_I2C_7, in FSM_I2C_TRIGGERS, is set.