SPRUGR9H November 2010 – April 2015 66AK2E05 , 66AK2H06 , 66AK2H12 , 66AK2H14 , 66AK2L06 , AM5K2E02 , AM5K2E04 , SM320C6678-HIREL , TMS320C6652 , TMS320C6654 , TMS320C6655 , TMS320C6657 , TMS320C6670 , TMS320C6671 , TMS320C6672 , TMS320C6674 , TMS320C6678
The Cycle Count Register (Figure 4-38) counts the number of cycles for which the PDSP has been enabled.
31 | 0 |
COUNT |
R/WC-0 |
Legend: R/W = Read/Write; - n = value after reset |
Bit | Field | Description |
---|---|---|
31-0 | COUNT | This value is incremented by 1 for every cycle during which the PDSP is enabled and the counter is enabled (both bits P_EN and C_EN set in the PDSP control register).
Counting halts while the PDSP is disabled or counter is disabled, and resumes when re-enabled. Counter clears the counter enable bit in the PDSP control register when the count reaches 0xFFFFFFFF. (Count does not wrap). The register can be read at any time. The register can be cleared when the counter or PDSP is disabled. Clearing this register also clears the PDSP Stall Count Register. |