SPRUGR9H November 2010 – April 2015 66AK2E05 , 66AK2H06 , 66AK2H12 , 66AK2H14 , 66AK2L06 , AM5K2E02 , AM5K2E04 , SM320C6678-HIREL , TMS320C6652 , TMS320C6654 , TMS320C6655 , TMS320C6657 , TMS320C6670 , TMS320C6671 , TMS320C6672 , TMS320C6674 , TMS320C6678
The Stall Count Register (Figure 4-39) counts cycles for which the PDSP has been enabled, but unable to fetch a new instruction. It is linked to the Cycle Count Register (0x0C) such that this register reflects the stall cycles measured over the same cycles as counted by the cycle count register. Thus the value of this register is always less than or equal to cycle count.
31 | 0 |
COUNT |
R-0 |
Legend: R = Read only; - n = value after reset |
Bit | Field | Description |
---|---|---|
31-0 | COUNT | This value is incremented by 1 for every cycle during which the PDSP is enabled and the counter is enabled (both bits P_EN and C_EN set in the PDSP control register), and the PDSP was unable to fetch a new instruction for any reason.
Counting halts while the PDSP is disabled or the counter is disabled, and resumes when re-enabled. The register can be read at any time. The register is cleared when PDSP Cycle Count Register is cleared. |