SPRUGR9H November 2010 – April 2015 66AK2E05 , 66AK2H06 , 66AK2H12 , 66AK2H14 , 66AK2L06 , AM5K2E02 , AM5K2E04 , SM320C6678-HIREL , TMS320C6652 , TMS320C6654 , TMS320C6655 , TMS320C6657 , TMS320C6670 , TMS320C6671 , TMS320C6672 , TMS320C6674 , TMS320C6678
Status Register 0 (Figure 4-47) provides status on the high-priority accumulator interrupts managed by the INTD. Reading this register returns a 1 bit for each interrupt that has been triggered. Writing to the register causes status bits to be cleared. Clearing status bits does not affect the count of interrupts in the Int Count Registers, nor does it clear the interrupt internally (the EOI register still needs to be written). In blocks where a single event can represent multiple grouped interrupts, these registers can be used to determine which interrupts have triggered. Because the QMSS does not group interrupts, this is needed only to keep clear which events have been processed (it is optional).
31 | 30 | ... | 1 | 0 |
INT31 | INT30 ... INT1 | INT0 |
R/W-0 | R/W-0 | R/W-0 |
Legend: R/W = Read/Write; - n = value after reset |
Bit | Field | Description |
---|---|---|
31 | INT31 | High Priority Accumulator Interrupt 31 status |
30
... 1 |
INT30
... INT1 |
High Priority Accumulator Interrupt n status |
0 | INT0 | High Priority Accumulator Interrupt 0 status |