SPRUGR9H November   2010  – April 2015 66AK2E05 , 66AK2H06 , 66AK2H12 , 66AK2H14 , 66AK2L06 , AM5K2E02 , AM5K2E04 , SM320C6678-HIREL , TMS320C6652 , TMS320C6654 , TMS320C6655 , TMS320C6657 , TMS320C6670 , TMS320C6671 , TMS320C6672 , TMS320C6674 , TMS320C6678

 

  1.   Preface
    1.     About This Manual
    2.     Trademarks
    3.     Notational Conventions
    4.     Related Documentation from Texas Instruments
  2. 1Introduction
    1. 1.1  Terminology Used in This Document
    2. 1.2  KeyStone I Features
    3. 1.3  KeyStone I Functional Block Diagram
    4. 1.4  KeyStone II Changes to QMSS
    5. 1.5  KeyStone II QMSS Modes of Use
      1. 1.5.1 Shared Mode
      2. 1.5.2 Split Mode
    6. 1.6  Overview
    7. 1.7  Queue Manager
    8. 1.8  Packet DMA (PKTDMA)
    9. 1.9  Navigator Cloud
    10. 1.10 Virtualization
    11. 1.11 ARM-DSP Shared Use
    12. 1.12 PDSP Firmware
  3. 2Operational Concepts
    1. 2.1 Packets
    2. 2.2 Queues
      1. 2.2.1 Packet Queuing
      2. 2.2.2 Packet De-queuing
      3. 2.2.3 Queue Proxy
    3. 2.3 Queue Types
      1. 2.3.1 Transmit Queues
      2. 2.3.2 Transmit Completion Queues
      3. 2.3.3 Receive Queues
      4. 2.3.4 Free Descriptor Queues (FDQ)
        1. 2.3.4.1 Host Packet Free Descriptors
        2. 2.3.4.2 Monolithic Free Descriptors
      5. 2.3.5 Queue Pend Queues
    4. 2.4 Descriptors
      1. 2.4.1 Host Packet
      2. 2.4.2 Host Buffer
      3. 2.4.3 Monolithic Packet
    5. 2.5 Packet DMA
      1. 2.5.1 Channels
      2. 2.5.2 RX Flows
    6. 2.6 Packet Transmission Overview
    7. 2.7 Packet Reception Overview
    8. 2.8 ARM Endianess
  4. 3Descriptor Layouts
    1. 3.1 Host Packet Descriptor
    2. 3.2 Host Buffer Descriptor
    3. 3.3 Monolithic Descriptor
  5. 4Registers
    1. 4.1 Queue Manager
      1. 4.1.1 Queue Configuration Region
        1. 4.1.1.1 Revision Register (0x00000000)
        2. 4.1.1.2 Queue Diversion Register (0x00000008)
        3. 4.1.1.3 Linking RAM Region 0 Base Address Register (0x0000000C)
        4. 4.1.1.4 Linking RAM Region 0 Size Register (0x00000010)
        5. 4.1.1.5 Linking RAM Region 1 Base Address Register (0x00000014)
        6. 4.1.1.6 Free Descriptor/Buffer Starvation Count Register N (0x00000020 + N×4)
      2. 4.1.2 Queue Status RAM
      3. 4.1.3 Descriptor Memory Setup Region
        1. 4.1.3.1 Memory Region R Base Address Register (0x00000000 + 16×R)
        2. 4.1.3.2 Memory Region R Start Index Register (0x00000004 + 16×R)
        3. 4.1.3.3 Memory Region R Descriptor Setup Register (0x00000008 + 16×R)
      4. 4.1.4 Queue Management/Queue Proxy Regions
        1. 4.1.4.1 Queue N Register A (0x00000000 + 16×N)
        2. 4.1.4.2 Queue N Register B (0x00000004 + 16×N)
        3. 4.1.4.3 Queue N Register C (0x00000008 + 16×N)
        4. 4.1.4.4 Queue N Register D (0x0000000C + 16×N)
      5. 4.1.5 Queue Peek Region
        1. 4.1.5.1 Queue N Status and Configuration Register A (0x00000000 + 16×N)
        2. 4.1.5.2 Queue N Status and Configuration Register B (0x00000004 + 16×N)
        3. 4.1.5.3 Queue N Status and Configuration Register C (0x00000008 + 16×N)
        4. 4.1.5.4 Queue N Status and Configuration Register D (0x0000000C + 16×N)
    2. 4.2 Packet DMA
      1. 4.2.1 Global Control Registers Region
        1. 4.2.1.1 Revision Register (0x00)
        2. 4.2.1.2 Performance Control Register (0x04)
        3. 4.2.1.3 Emulation Control Register (0x08)
        4. 4.2.1.4 Priority Control Register (0x0C)
        5. 4.2.1.5 QMn Base Address Register (0x10, 0x14, 0x18, 0x1c)
      2. 4.2.2 TX DMA Channel Configuration Region
        1. 4.2.2.1 TX Channel N Global Configuration Register A (0x000 + 32×N)
        2. 4.2.2.2 TX Channel N Global Configuration Register B (0x004 + 32×N)
      3. 4.2.3 RX DMA Channel Configuration Region
        1. 4.2.3.1 RX Channel N Global Configuration Register A (0x000 + 32×N)
      4. 4.2.4 RX DMA Flow Configuration Region
        1. 4.2.4.1 RX Flow N Configuration Register A (0x000 + 32×N)
        2. 4.2.4.2 RX Flow N Configuration Register B (0x004 + 32×N)
        3. 4.2.4.3 RX Flow N Configuration Register C (0x008 + 32×N)
        4. 4.2.4.4 RX Flow N Configuration Register D (0x00C + 32×N)
        5. 4.2.4.5 RX Flow N Configuration Register E (0x010 + 32×N)
        6. 4.2.4.6 RX Flow N Configuration Register F (0x014 + 32×N)
        7. 4.2.4.7 RX Flow N Configuration Register G (0x018 + 32×N)
        8. 4.2.4.8 RX Flow N Configuration Register H (0x01C + 32×N)
      5. 4.2.5 TX Scheduler Configuration Region
        1. 4.2.5.1 TX Channel N Scheduler Configuration Register (0x000 + 4×N)
    3. 4.3 QMSS PDSPs
      1. 4.3.1 Descriptor Accumulation Firmware
        1. 4.3.1.1 Command Buffer Interface
        2. 4.3.1.2 Global Timer Command Interface
        3. 4.3.1.3 Reclamation Queue Command Interface
        4. 4.3.1.4 Queue Diversion Command Interface
      2. 4.3.2 Quality of Service Firmware
        1. 4.3.2.1 QoS Algorithms
          1. 4.3.2.1.1 Modified Token Bucket Algorithm
        2. 4.3.2.2 Command Buffer Interface
        3. 4.3.2.3 QoS Firmware Commands
        4. 4.3.2.4 QoS Queue Record
        5. 4.3.2.5 QoS Cluster Record
        6. 4.3.2.6 RR-Mode QoS Cluster Record
        7. 4.3.2.7 SRIO Queue Monitoring
          1. 4.3.2.7.1 QoS SRIO Queue Monitoring Record
      3. 4.3.3 Open Event Machine Firmware
      4. 4.3.4 Interrupt Operation
        1. 4.3.4.1 Interrupt Handshaking
        2. 4.3.4.2 Interrupt Processing
        3. 4.3.4.3 Interrupt Generation
        4. 4.3.4.4 Stall Avoidance
      5. 4.3.5 QMSS PDSP Registers
        1. 4.3.5.1 Control Register (0x00000000)
        2. 4.3.5.2 Status Register (0x00000004)
        3. 4.3.5.3 Cycle Count Register (0x0000000C)
        4. 4.3.5.4 Stall Count Register (0x00000010)
    4. 4.4 QMSS Interrupt Distributor
      1. 4.4.1 INTD Register Region
        1. 4.4.1.1  Revision Register (0x00000000)
        2. 4.4.1.2  End Of Interrupt (EOI) Register (0x00000010)
        3. 4.4.1.3  Status Register 0 (0x00000200)
        4. 4.4.1.4  Status Register 1 (0x00000204)
        5. 4.4.1.5  Status Register 2 (0x00000208)
        6. 4.4.1.6  Status Register 3 (0x0000020c)
        7. 4.4.1.7  Status Register 4 (0x00000210)
        8. 4.4.1.8  Status Clear Register 0 (0x00000280)
        9. 4.4.1.9  Status Clear Register 1 (0x00000284)
        10. 4.4.1.10 Status Clear Register 4 (0x00000290)
        11. 4.4.1.11 Interrupt N Count Register (0x00000300 + 4xN)
  6. 5Mapping Information
    1. 5.1 Queue Maps
    2. 5.2 Interrupt Maps
      1. 5.2.1 KeyStone I TCI661x, C6670, C665x devices
      2. 5.2.2 KeyStone I TCI660x, C667x devices
      3. 5.2.3 KeyStone II devices
    3. 5.3 Memory Maps
      1. 5.3.1 QMSS Register Memory Map
      2. 5.3.2 KeyStone I PKTDMA Register Memory Map
      3. 5.3.3 KeyStone II PKTDMA Register Memory Map
    4. 5.4 Packet DMA Channel Map
  7. 6Programming Information
    1. 6.1 Programming Considerations
      1. 6.1.1 System Planning
      2. 6.1.2 Notification of Completed Work
    2. 6.2 Example Code
      1. 6.2.1 QMSS Initialization
      2. 6.2.2 PKTDMA Initialization
      3. 6.2.3 Normal Infrastructure DMA with Accumulation
      4. 6.2.4 Bypass Infrastructure notification with Accumulation
      5. 6.2.5 Channel Teardown
    3. 6.3 Programming Overrides
    4. 6.4 Programming Errors
    5. 6.5 Questions and Answers
  8. AExample Code Utility Functions
  9. BExample Code Types
  10. CExample Code Addresses
    1. C.1 KeyStone I Addresses:
    2. C.2 KeyStone II Addresses:
  11.   Revision History

B Example Code Types

The following type definitions are referenced by the programming examples above. For Big Endian applications, they should be compiled with _BIG_ENDIAN defined.

//Define the Accumulator Command Interface Structure #ifdef _BIG_ENDIAN typedef struct { uint32_t retrn_code:8; //0=idle, 1=success, 2-6=error uint32_t un1:8; uint32_t command:8; //0x80=disable, 0x81=enable, 0=firmware response uint32_t channel:8; //0 to 47 or 0 to 15 uint32_t queue_mask; //(multi-mode only) bit 0=qm_index queue uint32_t list_address; //address of Host ping-pong buffer uint32_t max_entries:16;//max entries per list uint32_t qm_index:16; //qnum to monitor (multiple of 32 for multimode) uint32_t un2:8; uint32_t cfg_un:2; uint32_t cfg_multi_q:1; //0=single queue mode, 1=multi queue mode uint32_t cfg_list_mode:1;//0=NULL terminate, 1=entry count mode uint32_t cfg_list_size:2;//0="D" Reg, 1="C+D" regs, 2="A+B+C+D" uint32_t cfg_int_delay:2;//0=none, 1=last int, 2=1st new, 3=last new uint32_t timer_count:16;//number of 25us timer ticks to delay int } Qmss_AccCmd; #else typedef struct { uint32_t channel:8; //0 to 47 or 0 to 15 uint32_t command:8; //0x80=disable, 0x81=enable, 0=firmware response uint32_t un1:8; uint32_t retrn_code:8; //0=idle, 1=success, 2-6=error uint32_t queue_mask; //(multi-mode only) bit 0=qm_index queue uint32_t list_address; //address of Host ping-pong buffer uint32_t qm_index:16; //qnum to monitor (multiple of 32 for multimode) uint32_t max_entries:16;//max entries per list uint32_t timer_count:16;//number of 25us timer ticks to delay int uint32_t cfg_int_delay:2;//0=none, 1=last int, 2=1st new, 3=last new uint32_t cfg_list_size:2;//0="D" Reg, 1="C+D" regs, 2="A+B+C+D" uint32_t cfg_list_mode:1;//0=NULL terminate, 1=entry count mode uint32_t cfg_multi_q:1; //0=single queue mode, 1=multi queue mode uint32_t cfg_un:2; uint32_t un2:8; } Qmss_AccCmd; #endif /*******************************************************************/ /* Define the bit and word layouts for the Host Packet Descriptor. */ /* For a Host Packet, this is used for the first descriptor only. */ /*******************************************************************/ #ifdef _BIG_ENDIAN typedef struct { /* word 0 */ uint32_t type_id : 2; //always 0x0 (Host Packet ID) uint32_t packet_type : 5; uint32_t reserved_w0 : 2; uint32_t ps_reg_loc : 1; //0=PS words in desc, 1=PS words in SOP buff uint32_t packet_length : 22; //in bytes (4M - 1 max) /* word 1 */ uint32_t src_tag_hi : 8; uint32_t src_tag_lo : 8; uint32_t dest_tag_hi : 8; uint32_t dest_tag_lo : 8; /* word 2 */ uint32_t epib : 1; //1=extended packet info block is present uint32_t reserved_w2 : 1; uint32_t psv_word_count : 6; //number of 32-bit PS data words uint32_t err_flags : 4; uint32_t ps_flags : 4; uint32_t return_policy : 1; //0=linked packet goes to pkt_return_qnum, //1=each descriptor goes to pkt_return_qnum uint32_t ret_push_policy : 1; //0=return to queue tail, 1=queue head uint32_t pkt_return_qmgr : 2; uint32_t pkt_return_qnum : 12; /* word 3 */ uint32_t reserved_w3 : 10; uint32_t buffer_len : 22; /* word 4 */ uint32_t buffer_ptr; /* word 5 */ uint32_t next_desc_ptr; /* word 6 */ uint32_t orig_buff0_pool : 4; uint32_t orig_buff0_refc : 6; uint32_t orig_buff0_len : 22; /* word 7 */ uint32_t orig_buff0_ptr; } MNAV_HostPacketDescriptor; #else typedef struct { /* word 0 */ uint32_t packet_length : 22; //in bytes (4M - 1 max) uint32_t ps_reg_loc : 1; //0=PS words in desc, 1=PS words in SOP buff uint32_t reserved_w0 : 2; uint32_t packet_type : 5; uint32_t type_id : 2; //always 0x0 (Host Packet ID) /* word 1 */ uint32_t dest_tag_lo : 8; uint32_t dest_tag_hi : 8; uint32_t src_tag_lo : 8; uint32_t src_tag_hi : 8; /* word 2 */ uint32_t pkt_return_qnum : 12; uint32_t pkt_return_qmgr : 2; uint32_t ret_push_policy : 1; //0=return to queue tail, 1=queue head uint32_t return_policy : 1; //0=linked packet goes to pkt_return_qnum, //1=each descriptor goes to pkt_return_qnum uint32_t ps_flags : 4; uint32_t err_flags : 4; uint32_t psv_word_count : 6; //number of 32-bit PS data words uint32_t reserved_w2 : 1; uint32_t epib : 1; //1=extended packet info block is present /* word 3 */ uint32_t buffer_len : 22; uint32_t reserved_w3 : 10; /* word 4 */ uint32_t buffer_ptr; /* word 5 */ uint32_t next_desc_ptr; /* word 6 */ uint32_t orig_buff0_len : 22; uint32_t orig_buff0_refc : 6; uint32_t orig_buff0_pool : 4; /* word 7 */ uint32_t orig_buff0_ptr; } MNAV_HostPacketDescriptor; #endif #define MNAV_HOST_PACKET_SIZE sizeof(MNAV_HostPacketDescriptor) /*******************************************************************/ /* Define the bit and word layouts for the Host Buffer Descriptor. */ /* For a Host Packet, this will used for secondary descriptors. */ /*******************************************************************/ #ifdef _BIG_ENDIAN typedef struct { /* word 0 */ uint32_t reserved_w0; /* word 1 */ uint32_t reserved_w1; /* word 2 */ uint32_t reserved_w2 : 17; uint32_t ret_push_policy : 1; //0=return to queue tail, 1=queue head uint32_t pkt_return_qmgr : 2; uint32_t pkt_return_qnum : 12; /* word 3 */ uint32_t reserved_w3 : 10; uint32_t buffer_len : 22; /* word 4 */ uint32_t buffer_ptr; /* word 5 */ uint32_t next_desc_ptr; /* word 6 */ uint32_t orig_buff0_pool : 4; uint32_t orig_buff0_refc : 6; uint32_t orig_buff0_len : 22; /* word 7 */ uint32_t orig_buff0_ptr; } MNAV_HostBufferDescriptor; #else typedef struct { /* word 0 */ uint32_t reserved_w0; /* word 1 */ uint32_t reserved_w1; /* word 2 */ uint32_t pkt_return_qnum : 12; uint32_t pkt_return_qmgr : 2; uint32_t ret_push_policy : 1; //0=return to queue tail, 1=queue head uint32_t reserved_w2 : 17; /* word 3 */ uint32_t buffer_len : 22; uint32_t reserved_w3 : 10; /* word 4 */ uint32_t buffer_ptr; /* word 5 */ uint32_t next_desc_ptr; /* word 6 */ uint32_t orig_buff0_len : 22; uint32_t orig_buff0_refc : 6; uint32_t orig_buff0_pool : 4; /* word 7 */ uint32_t orig_buff0_ptr; } MNAV_HostBufferDescriptor; #endif // Host Buffer packet size is always the same as Host Packet size /*********************************************************************/ /* Define the bit and word layouts for the Monolithic Pkt Descriptor.*/ /*********************************************************************/ #ifdef _BIG_ENDIAN typedef struct { /* word 0 */ uint32_t type_id : 2; //always 0x2 (Monolithic Packet ID) uint32_t packet_type : 5; uint32_t data_offset : 9; uint32_t packet_length : 16; //in bytes (65535 max) /* word 1 */ uint32_t src_tag_hi : 8; uint32_t src_tag_lo : 8; uint32_t dest_tag_hi : 8; uint32_t dest_tag_lo : 8; /* word 2 */ uint32_t epib : 1; //1=extended packet info block is present uint32_t reserved_w2 : 1; uint32_t psv_word_count : 6; //number of 32-bit PS data words uint32_t err_flags : 4; uint32_t ps_flags : 4; uint32_t reserved_w2b : 1; uint32_t ret_push_policy : 1; //0=return to queue tail, 1=queue head uint32_t pkt_return_qmgr : 2; uint32_t pkt_return_qnum : 12; } MNAV_MonolithicPacketDescriptor; #else typedef struct { /* word 0 */ uint32_t packet_length : 16; //in bytes (65535 max) uint32_t data_offset : 9; uint32_t packet_type : 5; uint32_t type_id : 2; //always 0x2 (Monolithic Packet ID) /* word 1 */ uint32_t dest_tag_lo : 8; uint32_t dest_tag_hi : 8; uint32_t src_tag_lo : 8; uint32_t src_tag_hi : 8; /* word 2 */ uint32_t pkt_return_qnum : 12; uint32_t pkt_return_qmgr : 2; uint32_t ret_push_policy : 1; //0=return to queue tail, 1=queue head uint32_t reserved_w2b : 1; uint32_t ps_flags : 4; uint32_t err_flags : 4; uint32_t psv_word_count : 6; //number of 32-bit PS data words uint32_t reserved_w2 : 1; uint32_t epib : 1; //1=extended packet info block is present } MNAV_MonolithicPacketDescriptor; #endif #define MNAV_MONO_PACKET_SIZE sizeof(MNAV_MonolithicPacketDescriptor) /*********************************************************************/ /* Define the word layout of the Extended Packet Info Block. It */ /* is optional and may follow Host Packet and Monolithic descriptors.*/ /*********************************************************************/ typedef struct { /* word 0 */ uint32_t timestamp; /* word 1 */ uint32_t sw_info0; /* word 2 */ uint32_t sw_info1; /* word 3 */ uint32_t sw_info2; } MNAV_ExtendedPacketInfoBlock;