SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
There are registers within the CTRL_MMR module that are used to dynamically change the DDR clock frequency to support LPDDR4 Frequency Set Point (FSP). These registers are shown in Table 5-8. For more information, see DDRSS Dynamic Frequency Change Interface in Memory Controllers.
Register Name |
---|
CHNG_DDR4_FSP_REQx |
CHNG_DDR4_FSP_ACKx |
DDR4_FSP_CLKCHNG_REQx |
DDR4_FSP_CLKCHNG_ACKx |
MULTI_DDR_CFGx |
DDR_CFG_LOAD |