SBAA607A December   2023  – January 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1 , AM263P4 , AMC1303M2520 , AMC1305L25 , AMC1306M25 , TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1 , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1 , TMS320F28075 , TMS320F28075-Q1 , TMS320F28076 , TMS320F28374D , TMS320F28374S , TMS320F28375D , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376D , TMS320F28376S , TMS320F28377D , TMS320F28377D-Q1 , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28378D , TMS320F28378S , TMS320F28379D , TMS320F28379D-Q1 , TMS320F28379S , TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DK-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Design Challenge With Digital Interface Timing Specifications
  6. 3Design Approach With Clock Edge Delay Compensation
    1. 3.1 Clock Signal Compensation With Software Configurable Phase Delay
    2. 3.2 Clock Signal Compensation With Hardware Configurable Phase Delay
    3. 3.3 Clock Signal Compensation by Clock Return
    4. 3.4 Clock Signal Compensation by Clock Inversion at the MCU
  7. 4Test and Validation
    1. 4.1 Test Equipment and Software
    2. 4.2 Testing of Clock Signal Compensation With Software Configurable Phase Delay
      1. 4.2.1 Test Setup
      2. 4.2.2 Test Measurement Results
    3. 4.3 Testing of Clock Signal Compensation by Clock Inversion at MCU
      1. 4.3.1 Test Setup
      2. 4.3.2 Test Measurement Results
        1. 4.3.2.1 Test Result – No Clock Inversion of Clock Input at GPIO123
        2. 4.3.2.2 Test Result – Clock Inversion of Clock Input at GPIO123
    4. 4.4 Digital Interface Timing Validation by Calculation Tool
      1. 4.4.1 Digital Interface With No Compensation Method
      2. 4.4.2 Commonly Used Method - Reduction of the Clock Frequency
      3. 4.4.3 Clock Edge Compensation With Software Configurable Phase Delay
  8. 5Conclusion
  9. 6References
  10. 7Revision History

3.1 Clock Signal Compensation With Software Configurable Phase Delay

Figure 3-1 shows the first compensation method, where an additional phase locked clock signal with a software configurable phase delay is used. For this compensation method the phase-shifted clock signal CLKOUT_delay is used as the clock input to SD0_CLK of the Sigma-Delta Filter Module (SDFM). For other types of Delta-Sigma Modulators and MCUs e.g. C2000 MCUs, the compensation method follows the same principle.

GUID-20231128-SS0I-KMJG-9MVJ-QNRQJ6PFV5VP-low.svgFigure 3-1 AMC1306M25 to AM243x MCU Interface With Software Configurable Clock Phase Delay

The implementation of a second phase-shifted clock signal offers the highest degree of freedom and user configurability. This means that various values for minimum hold time th(MIN) of various isolated modulators can be compensated by a simple change to the phase-shift value in software. The clock signals rising edge at the SD0_CLK input is phase-shifted such that the clocking signal complies with the data sampling point of the SDFM, as shown in Figure 3-2. The AM243x PRU_ICSSG PRU Timing Requirements in Sigma Delta Mode are 10 ns for minimum setup time tsu (SD_D-SD_CLK) (MIN) = 10 ns and 5 ns for minimum hold time th(SD_CLK-SD_D) (MIN) = 5 ns. This creates a need for compensation to maintain correct acquisition at the data input SDx_D with reference to the rising clock edge of the SDx_CLK signal as the AMC1306M25 minimum hold time th(MIN) is 3.5 ns, but 5 ns can be required. After this compensation method is applied, the 10-ns minimum setup and 5-ns hold timings for the Sigma Delta Mode of the AM243x PRU_ICSSG PRU timing requirements are met, see Figure 3-2.

GUID-20231128-SS0I-GXTM-VTFF-SHC4KFGVCCLF-low.svgFigure 3-2 AM243x SDFM Timing With 30-ns Phase-Shifted Clock Signal Input at SD0_CLK (GPIO1_1)