SBASB22 December   2025 ADS9324

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
  7. 6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Inputs
      2. 7.3.2  Input Clamp Protection Circuit
      3. 7.3.3  Analog Input Impedance
      4. 7.3.4  Programmable Gain Amplifier (PGA)
      5. 7.3.5  ADC Transfer Function
      6. 7.3.6  Reference
      7. 7.3.7  Open Wire Safe Mode
      8. 7.3.8  System Offset Calibration
      9. 7.3.9  System Gain Calibration
      10. 7.3.10 ADC Gain and Offset Error Calibration
      11. 7.3.11 Digital Filter
        1. 7.3.11.1 System Phase Calibration
        2. 7.3.11.2 Block Average Filter
        3. 7.3.11.3 Moving Average Filter
        4. 7.3.11.4 Low-Pass FIR Filter
      12. 7.3.12 Digital Window Comparator
      13. 7.3.13 Alarm Modes
      14. 7.3.14 Data Interface
        1. 7.3.14.1 ADC Channel Modes
        2. 7.3.14.2 Daisy Chain
        3. 7.3.14.3 Diagnostic Flags
        4. 7.3.14.4 ADC Output Data Randomizer
        5. 7.3.14.5 Test Patterns for Data Interface
        6. 7.3.14.6 Digital Output Drive Strength Control
        7. 7.3.14.7 Digital Output Delay Adjustment
    4. 7.4 Device Functional Modes
      1. 7.4.1 Reset
      2. 7.4.2 Normal Operation
      3. 7.4.3 Standby Mode
    5. 7.5 Programming
      1. 7.5.1 Register Write Operation
      2. 7.5.2 Register Read Operation
      3. 7.5.3 Initialization Example - Single Lane Mode on SDOUT
  9. 8 Register Maps
    1. 8.1 ADS93xx Common Registers
    2. 8.2 AIN1 - AIN8 Channel Registers
    3. 8.3 AIN9 - AIN16 Channel Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 16-Channel, Data Acquisition System (DAQ) for Power Automation
        1. 9.2.1.1 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Mechanical Data

7.3.2 Input Clamp Protection Circuit

As shown in Figure 7-1, the ADS9324 features an internal clamp protection circuit on each of the sixteen analog input channels. Use of external protection circuits is recommended as a secondary protection scheme to protect the device. Using external protection devices helps with protection against surges, electrostatic discharge (ESD), and electrical fast transient (EFT) conditions.

The ADS9324 allows each analog input to swing up to a maximum voltage of ±18V. In case of overvoltage condition, the input current increase linearly with the input voltage up to clamp voltage of ±105V. Figure 7-2 illustrates a typical current versus voltage characteristic curve for the input clamp. Beyond this voltage, the input clamp circuit turns on, and current increases exponentially.

ADS9324 Input Clamp Protection Profile: Input Current vs Input Voltage Figure 7-2 Input Clamp Protection Profile: Input Current vs Input Voltage

For input voltages exceeding the maximum input voltage ±18V, make sure that input current never exceeds the absolute maximum rating (see the Section 5.1 table) of ±10mA to prevent any damage to the device. Figure 7-3 shows that a small series resistor placed in series with the analog inputs is an effective way to limit the input current. In addition to limiting the input current, this resistor can also provide an antialiasing, low-pass filter when coupled with a capacitor. To maintain the dc accuracy of the system, matching the external source impedance on the AINnP input pin with an equivalent resistance on the AINnM pin is recommended. This matching helps to cancel any additional offset error contributed by the external resistance.

ADS9324 Matching Input Resistors on the Analog Inputs of Devices Figure 7-3 Matching Input Resistors on the Analog Inputs of Devices

The input overvoltage protection clamp on the ADS9324 is intended to control transient excursions on the input pins. Leaving the device in a state such that the clamp circuit is activated for extended periods of time in normal or power-down mode is not recommended because this fault condition can degrade device performance and reliability.