SBASB93 June   2026 ADS9308V8I

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Current Sense Programmable Gain Amplifier
      2. 6.3.2 Voltage Sense Programmable Gain Amplifier (VPGA)
      3. 6.3.3 ADC Transfer Function
      4. 6.3.4 Reference
      5. 6.3.5 Digital Averaging Filter
      6. 6.3.6 Data Interface
        1. 6.3.6.1 ADC Channel Modes
    4. 6.4 Device Functional Modes
      1. 6.4.1 Reset
      2. 6.4.2 Normal Operation
      3. 6.4.3 Standby Mode
    5. 6.5 Programming
      1. 6.5.1 Register Write Operation
      2. 6.5.2 Register Read Operation
      3. 6.5.3 Initialization Sequence
    6. 6.6 Register Maps
      1. 6.6.1 ADS93x8V8I Common Registers
      2. 6.6.2 IS1 - IS8 Channel Registers
      3. 6.6.3 VS1 - VS8 Channel Registers
  8. 7 Application and Implementation
    1. 7.1 Typical Application
      1. 7.1.1 Multichannel Lithium-ion cell formation and test
    2. 7.2 Power Supply Recommendations
    3. 7.3 Layout
      1. 7.3.1 Layout Guidelines
      2. 7.3.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Tape and Reel Information
    2. 10.2 Mechanical Data

6.3.6.1 ADC Channel Modes

ADS93x8V8I contains a digital feature to select the number of ADC channels on the data interface. Table 6-6 shows the possible combinations supported in the device. In all modes, the lowest channel number gets transmitted first. Figure 6-7 shows an 8-channel ADC data read mode when ADC_CH_SEL = 0xxb.

Table 6-6 ADC Channel Modes
ADC_NUM_SEL ADC_CH_SEL ADC CHANNELS REPORTED ADC OUTPUT
00b (Default) xxxb 16 (Default) IS1, IS2, IS3, IS4, IS5, IS6, IS7, IS8, VS1, VS2, VS3, VS4, VS5 VS6, VS7, VS8
01b 0xxb 8 IS1, IS2, IS3, IS4, VS5, VS6, VS7, VS8
01b 1xxb 8 IS5, IS6, IS7, IS8, VS1, VS2, VS3, VS4
10b 00xb 4 IS1, IS2, VS7, VS8
10b 01xb 4 IS3, IS4, VS5, VS6
10b 10xb 4 IS5, IS6, VS3, VS4
10b 11xb 4 IS7, IS8, VS1, VS2
11b 000b 2 IS1, VS8
11b 001b 2 IS2, VS7
11b 010b 2 IS3, VS6
11b 011b 2 IS4, VS5
11b 100b 2 IS5, VS4
11b 101b 2 IS6, VS3
11b 110b 2 IS7, VS2
11b 111b 2 IS8, VS1
ADS9308V8I 8 Channel ADC Data Read, ADC_NUM_SEL =01b, ADC_CH_SEL = 0xxb Figure 6-6 8 Channel ADC Data Read, ADC_NUM_SEL =01b, ADC_CH_SEL = 0xxb
ADS9308V8I 8 Channel ADC Data Read, ADC_NUM_SEL =01b, ADC_CH_SEL = 1xxb Figure 6-7 8 Channel ADC Data Read, ADC_NUM_SEL =01b, ADC_CH_SEL = 1xxb