SBASB93 June   2026 ADS9308V8I

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Current Sense Programmable Gain Amplifier
      2. 6.3.2 Voltage Sense Programmable Gain Amplifier (VPGA)
      3. 6.3.3 ADC Transfer Function
      4. 6.3.4 Reference
      5. 6.3.5 Digital Averaging Filter
      6. 6.3.6 Data Interface
        1. 6.3.6.1 ADC Channel Modes
    4. 6.4 Device Functional Modes
      1. 6.4.1 Reset
      2. 6.4.2 Normal Operation
      3. 6.4.3 Standby Mode
    5. 6.5 Programming
      1. 6.5.1 Register Write Operation
      2. 6.5.2 Register Read Operation
      3. 6.5.3 Initialization Sequence
    6. 6.6 Register Maps
      1. 6.6.1 ADS93x8V8I Common Registers
      2. 6.6.2 IS1 - IS8 Channel Registers
      3. 6.6.3 VS1 - VS8 Channel Registers
  8. 7 Application and Implementation
    1. 7.1 Typical Application
      1. 7.1.1 Multichannel Lithium-ion cell formation and test
    2. 7.2 Power Supply Recommendations
    3. 7.3 Layout
      1. 7.3.1 Layout Guidelines
      2. 7.3.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Tape and Reel Information
    2. 10.2 Mechanical Data

6.5.3 Initialization Sequence

As shown in Section 6.5.3, initialize the ADS93x8V8I with a sequence of register writes after device power up or reset. Step 2 to Step 9 initializations are required for pre-production sample units.

Table 6-9 ADS93x8V8I Initialization Example
STEP NUMBER REGISTER DESCRIPTION
SDIN[23:16] = REG_ADDR SDIN[15:0] = REG_ADDR DATA
1 0x01 0x0002 Software reset
Wait 1ms
2 0x02 0x0001 Selects ADS9308V8I common register bank
3 0x14 0x0040 Minimum OSR supported is 8. User can program OSR multiple of 8, i.e. 16, 32, 64 and 128.
4 0x14 0x0041 Set SYSREF to 1b
Wait 10μs
5 0x14 0x0040 Set SYSREF to 0b
6 0x02 0x0002 Selects ADS9308V8I INA register bank
7 0x3A 0x0400 Configures the INA
8 0x02 0x0001 Selects ADS9308V8I common register bank
9 0x11 0x1000 Configures the INA. Set this to 0x1000 for maximum ODR of 125kSPS. For ODR less than equal to 62.5kSPS, program this field to 0x4000.
10 [user dependent] 0x0A 0x003A User programs this register based on system requirements. 0x003A selects ADC conversion data size of 24b, and 1-lane mode data output on SDOUT pin.