SBASB93 June   2026 ADS9308V8I

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Current Sense Programmable Gain Amplifier
      2. 6.3.2 Voltage Sense Programmable Gain Amplifier (VPGA)
      3. 6.3.3 ADC Transfer Function
      4. 6.3.4 Reference
      5. 6.3.5 Digital Averaging Filter
      6. 6.3.6 Data Interface
        1. 6.3.6.1 ADC Channel Modes
    4. 6.4 Device Functional Modes
      1. 6.4.1 Reset
      2. 6.4.2 Normal Operation
      3. 6.4.3 Standby Mode
    5. 6.5 Programming
      1. 6.5.1 Register Write Operation
      2. 6.5.2 Register Read Operation
      3. 6.5.3 Initialization Sequence
    6. 6.6 Register Maps
      1. 6.6.1 ADS93x8V8I Common Registers
      2. 6.6.2 IS1 - IS8 Channel Registers
      3. 6.6.3 VS1 - VS8 Channel Registers
  8. 7 Application and Implementation
    1. 7.1 Typical Application
      1. 7.1.1 Multichannel Lithium-ion cell formation and test
    2. 7.2 Power Supply Recommendations
    3. 7.3 Layout
      1. 7.3.1 Layout Guidelines
      2. 7.3.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Tape and Reel Information
    2. 10.2 Mechanical Data

6.6.3 VS1 - VS8 Channel Registers

Table 6-74 lists the memory-mapped registers for the VS1 - VS8 Channel registers. All register offset addresses not listed in Table 6-74 should be considered as reserved locations and the register contents should not be modified.

Table 6-74 VS1 - VS8 Channel
AddressAcronymBit 15Bit 14Bit 13Bit 12Bit 11Bit 10Bit 9Bit 8
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
0x08PGA_CONFIG_VS7_8CME_CORR_EN_VS7CM_RANGE_VS7[2:0]RESERVEDINPUT_RANGE_VS7[2:0]
CME_CORR_EN_VS8CM_RANGE_VS8[2:0]RESERVEDINPUT_RANGE_VS8[2:0]
0x09PGA_CONFIG_VS5_6CME_CORR_EN_VS5CM_RANGE_VS5[2:0]RESERVEDINPUT_RANGE_VS5[2:0]
CME_CORR_EN_VS6CM_RANGE_VS6[2:0]RESERVEDINPUT_RANGE_VS6[2:0]
0x0APGA_CONFIG_VS3_4CME_CORR_EN_VS3CM_RANGE_VS3[2:0]RESERVEDINPUT_RANGE_VS3[2:0]
CME_CORR_EN_VS4CM_RANGE_VS4[2:0]RESERVEDINPUT_RANGE_VS4[2:0]
0x0BPGA_CONFIG_VS1_2CME_CORR_EN_VS1CM_RANGE_VS1[2:0]RESERVEDINPUT_RANGE_VS1[2:0]
CME_CORR_EN_VS2CM_RANGE_VS2[2:0]RESERVEDINPUT_RANGE_VS2[2:0]
0x0CPGA_BW_SEL_VS1_8PGA_BW_SEL_VS1[1:0]PGA_BW_SEL_VS2[1:0]PGA_BW_SEL_VS3[1:0]PGA_BW_SEL_VS4[1:0]
PGA_BW_SEL_VS5[1:0]PGA_BW_SEL_VS6[1:0]PGA_BW_SEL_VS7[1:0]PGA_BW_SEL_VS8[1:0]
0x11OFS_VS8RESERVEDOFS_VS8[9:0]
OFS_VS8[9:0]
0x12OFS_VS7RESERVEDOFS_VS7[9:0]
OFS_VS7[9:0]
0x13OFS_VS6RESERVEDOFS_VS6[9:0]
OFS_VS6[9:0]
0x14OFS_VS5RESERVEDOFS_VS5[9:0]
OFS_VS5[9:0]
0x15OFS_VS4RESERVEDOFS_VS4[9:0]
OFS_VS4[9:0]
0x16OFS_VS3RESERVEDOFS_VS3[9:0]
OFS_VS3[9:0]
0x17OFS_VS2RESERVEDOFS_VS2[9:0]
OFS_VS2[9:0]
0x18OFS_VS1RESERVEDOFS_VS1[9:0]
OFS_VS1[9:0]
0x19GAN_VS8RESERVEDGAN_VS8[13:0]
GAN_VS8[13:0]
0x1AGAN_VS7RESERVEDGAN_VS7[13:0]
GAN_VS7[13:0]
0x1BGAN_VS6RESERVEDGAN_VS6[13:0]
GAN_VS6[13:0]
0x1CGAN_VS5RESERVEDGAN_VS5[13:0]
GAN_VS5[13:0]
0x1DGAN_VS4RESERVEDGAN_VS4[13:0]
GAN_VS4[13:0]
0x1EGAN_VS3RESERVEDGAN_VS3[13:0]
GAN_VS3[13:0]
0x1FGAN_VS2RESERVEDGAN_VS2[13:0]
GAN_VS2[13:0]
0x20GAN_VS1RESERVEDGAN_VS1[13:0]
GAN_VS1[13:0]
0x21DWC_CFGDWC_RSTRESERVEDDWC_GLITCH_FILT[3:0]
DWC_EN_VS1DWC_EN_VS2DWC_EN_VS3DWC_EN_VS4DWC_EN_VS5DWC_EN_VS6DWC_EN_VS7DWC_EN_VS8
0x22DWC_TH_VS8HIGH_TH_VS8[7:0]
LOW_TH_VS8[7:0]
0x23DWC_TH_VS7HIGH_TH_VS7[7:0]
LOW_TH_VS7[7:0]
0x24DWC_TH_VS6HIGH_TH_VS6[7:0]
LOW_TH_VS6[7:0]
0x25DWC_TH_VS5HIGH_TH_VS5[7:0]
LOW_TH_VS5[7:0]
0x26DWC_TH_VS4HIGH_TH_VS4[7:0]
LOW_TH_VS4[7:0]
0x27DWC_TH_VS3HIGH_TH_VS3[7:0]
LOW_TH_VS3[7:0]
0x28DWC_TH_VS2HIGH_TH_VS2[7:0]
LOW_TH_VS2[7:0]
0x29DWC_TH_VS1HIGH_TH_VS1[7:0]
LOW_TH_VS1[7:0]
0x2ADWC_HYS_VS7_8HYS_VS8[7:0]
HYS_VS7[7:0]
0x2BDWC_HYS_VS5_6HYS_VS6[7:0]
HYS_VS5[7:0]
0x2CDWC_HYS_VS3_4HYS_VS4[7:0]
HYS_VS3[7:0]
0x2DDWC_HYS_VS1_2HYS_VS2[7:0]
HYS_VS1[7:0]
0x2ETP_CFGRESERVED
RESERVEDTP_MODE[2:0]RESERVEDTP_DIS_IDXTP_UP_DN_ENTP_EN
0x2FTP_VS8TP_VS8[15:0]
TP_VS8[15:0]
0x30TP_VS7TP_VS7[15:0]
TP_VS7[15:0]
0x31TP_VS6TP_VS6[15:0]
TP_VS6[15:0]
0x32TP_VS5TP_VS5[15:0]
TP_VS5[15:0]
0x33TP_VS4TP_VS4[15:0]
TP_VS4[15:0]
0x34TP_VS3TP_VS3[15:0]
TP_VS3[15:0]
0x35TP_VS2TP_VS2[15:0]
TP_VS2[15:0]
0x36TP_VS1TP_VS1[15:0]
TP_VS1[15:0]
0x37GEN_CFG1RESERVED
RESERVEDOFS_CORR_ENGAN_CORR_EN
0x3EDWC_FLAG_VS1_8HIGH_FLAG_VS1HIGH_FLAG_VS2HIGH_FLAG_VS3HIGH_FLAG_VS4HIGH_FLAG_VS5HIGH_FLAG_VS6HIGH_FLAG_VS7HIGH_FLAG_VS8
LOW_FLAG_VS1LOW_FLAG_VS2LOW_FLAG_VS3LOW_FLAG_VS4LOW_FLAG_VS5LOW_FLAG_VS6LOW_FLAG_VS7LOW_FLAG_VS8

Complex bit access types are encoded to fit into small table cells. Table 6-75 shows the codes that are used for access types in this section.

Table 6-75 VS1 - VS8 Channel Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

6.6.3.1 PGA_CONFIG_VS7_8 Register (Address = 0x08) [Reset = 0x0000]

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Figure 6-70 PGA_CONFIG_VS7_8 Register
15141312111098
CME_CORR_EN_VS7CM_RANGE_VS7[2:0]RESERVEDINPUT_RANGE_VS7[2:0]
R/W-0bR/W-000bR/W-0bR/W-000b
76543210
CME_CORR_EN_VS8CM_RANGE_VS8[2:0]RESERVEDINPUT_RANGE_VS8[2:0]
R/W-0bR/W-000bR/W-0bR/W-000b
Table 6-76 PGA_CONFIG_VS7_8 Register Field Descriptions
BitFieldTypeResetDescription
15CME_CORR_EN_VS7R/W0bCommon mode error correction enable.
14:12CM_RANGE_VS7[2:0]R/W000bSelect input signal type.
  • 000b = Differential (±12.5V CM Range)
  • 101b = Single ended
  • 110b = Single ended open wire safe
11RESERVEDR/W0bReserved. Do not change from the default reset value.
10:8INPUT_RANGE_VS7[2:0]R/W000bVS7 analog input range selection.
  • 000b = ±5V
  • 001b = ±25V
  • 010b = ±2.5V
  • 011b = ±6.25V
  • 100b = ±10V
  • 101b = ±12.5V
  • 110b = ±50V
  • 111b = Reserved
7CME_CORR_EN_VS8R/W0bCommon mode error correction enable.
6:4CM_RANGE_VS8[2:0]R/W000bSelect input signal type.
  • 000b = Differential (±12.5V CM Range)
  • 101b = Single ended
  • 110b = Single ended open wire safe
3RESERVEDR/W0bReserved. Do not change from the default reset value.
2:0INPUT_RANGE_VS8[2:0]R/W000bVS8 analog input range selection.
  • 000b = ±5V
  • 001b = ±25V
  • 010b = ±2.5V
  • 011b = ±6.25V
  • 100b = ±10V
  • 101b = ±12.5V
  • 110b = ±50V
  • 111b = Reserved

6.6.3.2 PGA_CONFIG_VS5_6 Register (Address = 0x09) [Reset = 0x0000]

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Figure 6-71 PGA_CONFIG_VS5_6 Register
15141312111098
CME_CORR_EN_VS5CM_RANGE_VS5[2:0]RESERVEDINPUT_RANGE_VS5[2:0]
R/W-0bR/W-000bR/W-0bR/W-000b
76543210
CME_CORR_EN_VS6CM_RANGE_VS6[2:0]RESERVEDINPUT_RANGE_VS6[2:0]
R/W-0bR/W-000bR/W-0bR/W-000b
Table 6-77 PGA_CONFIG_VS5_6 Register Field Descriptions
BitFieldTypeResetDescription
15CME_CORR_EN_VS5R/W0bCommon mode error correction enable.
14:12CM_RANGE_VS5[2:0]R/W000bSelect input signal type.
  • 000b = Differential (±12.5V CM Range)
  • 101b = Single ended
  • 110b = Single ended open wire safe
11RESERVEDR/W0bReserved. Do not change from the default reset value.
10:8INPUT_RANGE_VS5[2:0]R/W000bVS5 analog input range selection.
  • 000b = ±5V
  • 001b = ±25V
  • 010b = ±2.5V
  • 011b = ±6.25V
  • 100b = ±10V
  • 101b = ±12.5V
  • 110b = ±50V
  • 111b = Reserved
7CME_CORR_EN_VS6R/W0bCommon mode error correction enable.
6:4CM_RANGE_VS6[2:0]R/W000bSelect input signal type.
  • 000b = Differential (±12.5V CM Range)
  • 101b = Single ended
  • 110b = Single ended open wire safe
3RESERVEDR/W0bReserved. Do not change from the default reset value.
2:0INPUT_RANGE_VS6[2:0]R/W000bVS6 analog input range selection.
  • 000b = ±5V
  • 001b = ±25V
  • 010b = ±2.5V
  • 011b = ±6.25V
  • 100b = ±10V
  • 101b = ±12.5V
  • 110b = ±50V
  • 111b = Reserved

6.6.3.3 PGA_CONFIG_VS3_4 Register (Address = 0x0A) [Reset = 0x0000]

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Figure 6-72 PGA_CONFIG_VS3_4 Register
15141312111098
CME_CORR_EN_VS3CM_RANGE_VS3[2:0]RESERVEDINPUT_RANGE_VS3[2:0]
R/W-0bR/W-000bR/W-0bR/W-000b
76543210
CME_CORR_EN_VS4CM_RANGE_VS4[2:0]RESERVEDINPUT_RANGE_VS4[2:0]
R/W-0bR/W-000bR/W-0bR/W-000b
Table 6-78 PGA_CONFIG_VS3_4 Register Field Descriptions
BitFieldTypeResetDescription
15CME_CORR_EN_VS3R/W0bCommon mode error correction enable.
14:12CM_RANGE_VS3[2:0]R/W000bSelect input signal type.
  • 000b = Differential (±12.5V CM Range)
  • 101b = Single ended
  • 110b = Single ended open wire safe
11RESERVEDR/W0bReserved. Do not change from the default reset value.
10:8INPUT_RANGE_VS3[2:0]R/W000bVS3 analog input range selection.
  • 000b = ±5V
  • 001b = ±25V
  • 010b = ±2.5V
  • 011b = ±6.25V
  • 100b = ±10V
  • 101b = ±12.5V
  • 110b = ±50V
  • 111b = Reserved
7CME_CORR_EN_VS4R/W0bCommon mode error correction enable.
6:4CM_RANGE_VS4[2:0]R/W000bSelect input signal type.
  • 000b = Differential (±12.5V CM Range)
  • 101b = Single ended
  • 110b = Single ended open wire safe
3RESERVEDR/W0bReserved. Do not change from the default reset value.
2:0INPUT_RANGE_VS4[2:0]R/W000bVS4 analog input range selection.
  • 000b = ±5V
  • 001b = ±25V
  • 010b = ±2.5V
  • 011b = ±6.25V
  • 100b = ±10V
  • 101b = ±12.5V
  • 110b = ±50V
  • 111b = Reserved

6.6.3.4 PGA_CONFIG_VS1_2 Register (Address = 0x0B) [Reset = 0x0000]

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Figure 6-73 PGA_CONFIG_VS1_2 Register
15141312111098
CME_CORR_EN_VS1CM_RANGE_VS1[2:0]RESERVEDINPUT_RANGE_VS1[2:0]
R/W-0bR/W-000bR/W-0bR/W-000b
76543210
CME_CORR_EN_VS2CM_RANGE_VS2[2:0]RESERVEDINPUT_RANGE_VS2[2:0]
R/W-0bR/W-000bR/W-0bR/W-000b
Table 6-79 PGA_CONFIG_VS1_2 Register Field Descriptions
BitFieldTypeResetDescription
15CME_CORR_EN_VS1R/W0bCommon mode error correction enable.
14:12CM_RANGE_VS1[2:0]R/W000bSelect input signal type.
  • 000b = Differential (±12.5V CM Range)
  • 101b = Single ended
  • 110b = Single ended open wire safe
11RESERVEDR/W0bReserved. Do not change from the default reset value.
10:8INPUT_RANGE_VS1[2:0]R/W000bVS1 analog input range selection.
  • 000b = ±5V
  • 001b = ±25V
  • 010b = ±2.5V
  • 011b = ±6.25V
  • 100b = ±10V
  • 101b = ±12.5V
  • 110b = ±50V
  • 111b = Reserved
7CME_CORR_EN_VS2R/W0bCommon mode error correction enable.
6:4CM_RANGE_VS2[2:0]R/W000bSelect input signal type.
  • 000b = Differential (±12.5V CM Range)
  • 101b = Single ended
  • 110b = Single ended open wire safe
3RESERVEDR/W0bReserved. Do not change from the default reset value.
2:0INPUT_RANGE_VS2[2:0]R/W000bVS2 analog input range selection.
  • 000b = ±5V
  • 001b = ±25V
  • 010b = ±2.5V
  • 011b = ±6.25V
  • 100b = ±10V
  • 101b = ±12.5V
  • 110b = ±50V
  • 111b = Reserved

6.6.3.5 PGA_BW_SEL_VS1_8 Register (Address = 0x0C) [Reset = 0x0000]

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Figure 6-74 PGA_BW_SEL_VS1_8 Register
15141312111098
PGA_BW_SEL_VS1[1:0]PGA_BW_SEL_VS2[1:0]PGA_BW_SEL_VS3[1:0]PGA_BW_SEL_VS4[1:0]
R/W-00bR/W-00bR/W-00bR/W-00b
76543210
PGA_BW_SEL_VS5[1:0]PGA_BW_SEL_VS6[1:0]PGA_BW_SEL_VS7[1:0]PGA_BW_SEL_VS8[1:0]
R/W-00bR/W-00bR/W-00bR/W-00b
Table 6-80 PGA_BW_SEL_VS1_8 Register Field Descriptions
BitFieldTypeResetDescription
15:14PGA_BW_SEL_VS1[1:0]R/W00bVS1 analog low pass filter configuration control.
  • 00b = Low-bandwidth
  • 01b = Wide-bandwidth
  • 10b = Reserved
  • 11b = Reserved
13:12PGA_BW_SEL_VS2[1:0]R/W00bVS2 analog low pass filter configuration control.
  • 00b = Low-bandwidth
  • 01b = Wide-bandwidth
  • 10b = Reserved
  • 11b = Reserved
11:10PGA_BW_SEL_VS3[1:0]R/W00bVS3 analog low pass filter configuration control.
  • 00b = Low-bandwidth
  • 01b = Wide-bandwidth
  • 10b = Reserved
  • 11b = Reserved
9:8PGA_BW_SEL_VS4[1:0]R/W00bVS4 analog low pass filter configuration control.
  • 00b = Low-bandwidth
  • 01b = Wide-bandwidth
  • 10b = Reserved
  • 11b = Reserved
7:6PGA_BW_SEL_VS5[1:0]R/W00bVS5 analog low pass filter configuration control.
  • 00b = Low-bandwidth
  • 01b = Wide-bandwidth
  • 10b = Reserved
  • 11b = Reserved
5:4PGA_BW_SEL_VS6[1:0]R/W00bVS6 analog low pass filter configuration control.
  • 00b = Low-bandwidth
  • 01b = Wide-bandwidth
  • 10b = Reserved
  • 11b = Reserved
3:2PGA_BW_SEL_VS7[1:0]R/W00bVS7 analog low pass filter configuration control.
  • 00b = Low-bandwidth
  • 01b = Wide-bandwidth
  • 10b = Reserved
  • 11b = Reserved
1:0PGA_BW_SEL_VS8[1:0]R/W00bVS8 analog low pass filter configuration control.
  • 00b = Low-bandwidth
  • 01b = Wide-bandwidth
  • 10b = Reserved
  • 11b = Reserved

6.6.3.6 OFS_VS8 Register (Address = 0x11) [Reset = 0x0000]

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Figure 6-75 OFS_VS8 Register
15141312111098
RESERVEDOFS_VS8[9:0]
R/W-000000bR/W-0000000000b
76543210
OFS_VS8[9:0]
R/W-0000000000b
Table 6-81 OFS_VS8 Register Field Descriptions
BitFieldTypeResetDescription
15:10RESERVEDR/W000000bReserved. Do not change from the default reset value.
9:0OFS_VS8[9:0]R/W0000000000bOffset correction register for VS8.
The offset value is in two's complement representation and is added to the conversion result. The offset operation precedes the gain operation.

6.6.3.7 OFS_VS7 Register (Address = 0x12) [Reset = 0x0000]

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Figure 6-76 OFS_VS7 Register
15141312111098
RESERVEDOFS_VS7[9:0]
R/W-000000bR/W-0000000000b
76543210
OFS_VS7[9:0]
R/W-0000000000b
Table 6-82 OFS_VS7 Register Field Descriptions
BitFieldTypeResetDescription
15:10RESERVEDR/W000000bReserved. Do not change from the default reset value.
9:0OFS_VS7[9:0]R/W0000000000bOffset correction register for VS7.
The offset value is in two's complement representation and is added to the conversion result. The offset operation precedes the gain operation.

6.6.3.8 OFS_VS6 Register (Address = 0x13) [Reset = 0x0000]

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Figure 6-77 OFS_VS6 Register
15141312111098
RESERVEDOFS_VS6[9:0]
R/W-000000bR/W-0000000000b
76543210
OFS_VS6[9:0]
R/W-0000000000b
Table 6-83 OFS_VS6 Register Field Descriptions
BitFieldTypeResetDescription
15:10RESERVEDR/W000000bReserved. Do not change from the default reset value.
9:0OFS_VS6[9:0]R/W0000000000bOffset correction register for VS6.
The offset value is in two's complement representation and is added to the conversion result. The offset operation precedes the gain operation.

6.6.3.9 OFS_VS5 Register (Address = 0x14) [Reset = 0x0000]

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Figure 6-78 OFS_VS5 Register
15141312111098
RESERVEDOFS_VS5[9:0]
R/W-000000bR/W-0000000000b
76543210
OFS_VS5[9:0]
R/W-0000000000b
Table 6-84 OFS_VS5 Register Field Descriptions
BitFieldTypeResetDescription
15:10RESERVEDR/W000000bReserved. Do not change from the default reset value.
9:0OFS_VS5[9:0]R/W0000000000bOffset correction register for VS5.
The offset value is in two's complement representation and is added to the conversion result. The offset operation precedes the gain operation.

6.6.3.10 OFS_VS4 Register (Address = 0x15) [Reset = 0x0000]

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Figure 6-79 OFS_VS4 Register
15141312111098
RESERVEDOFS_VS4[9:0]
R/W-000000bR/W-0000000000b
76543210
OFS_VS4[9:0]
R/W-0000000000b
Table 6-85 OFS_VS4 Register Field Descriptions
BitFieldTypeResetDescription
15:10RESERVEDR/W000000bReserved. Do not change from the default reset value.
9:0OFS_VS4[9:0]R/W0000000000bOffset correction register for VS4.
The offset value is in two's complement representation and is added to the conversion result. The offset operation precedes the gain operation.

6.6.3.11 OFS_VS3 Register (Address = 0x16) [Reset = 0x0000]

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Figure 6-80 OFS_VS3 Register
15141312111098
RESERVEDOFS_VS3[9:0]
R/W-000000bR/W-0000000000b
76543210
OFS_VS3[9:0]
R/W-0000000000b
Table 6-86 OFS_VS3 Register Field Descriptions
BitFieldTypeResetDescription
15:10RESERVEDR/W000000bReserved. Do not change from the default reset value.
9:0OFS_VS3[9:0]R/W0000000000bOffset correction register for VS3.
The offset value is in two's complement representation and is added to the conversion result. The offset operation precedes the gain operation.

6.6.3.12 OFS_VS2 Register (Address = 0x17) [Reset = 0x0000]

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Figure 6-81 OFS_VS2 Register
15141312111098
RESERVEDOFS_VS2[9:0]
R/W-000000bR/W-0000000000b
76543210
OFS_VS2[9:0]
R/W-0000000000b
Table 6-87 OFS_VS2 Register Field Descriptions
BitFieldTypeResetDescription
15:10RESERVEDR/W000000bReserved. Do not change from the default reset value.
9:0OFS_VS2[9:0]R/W0000000000bOffset correction register for VS2.
The offset value is in two's complement representation and is added to the conversion result. The offset operation precedes the gain operation.

6.6.3.13 OFS_VS1 Register (Address = 0x18) [Reset = 0x0000]

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Figure 6-82 OFS_VS1 Register
15141312111098
RESERVEDOFS_VS1[9:0]
R/W-000000bR/W-0000000000b
76543210
OFS_VS1[9:0]
R/W-0000000000b
Table 6-88 OFS_VS1 Register Field Descriptions
BitFieldTypeResetDescription
15:10RESERVEDR/W000000bReserved. Do not change from the default reset value.
9:0OFS_VS1[9:0]R/W0000000000bOffset correction register for VS1.
The offset value is in two's complement representation and is added to the conversion result. The offset operation precedes the gain operation.

6.6.3.14 GAN_VS8 Register (Address = 0x19) [Reset = 0x0000]

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Figure 6-83 GAN_VS8 Register
15141312111098
RESERVEDGAN_VS8[13:0]
R/W-00bR/W-00000000000000b
76543210
GAN_VS8[13:0]
R/W-00000000000000b
Table 6-89 GAN_VS8 Register Field Descriptions
BitFieldTypeResetDescription
15:14RESERVEDR/W00bReserved. Do not change from the default reset value.
13:0GAN_VS8[13:0]R/W00000000000000bGain correction register for VS8.
The gain correction value is in two's complement representation, and is done after offset operation. During gain operation, the conversion data are multiplied by (1 + GAN_VSn[13:0] / 10000h).

6.6.3.15 GAN_VS7 Register (Address = 0x1A) [Reset = 0x0000]

Return to the Summary Table.

Figure 6-84 GAN_VS7 Register
15141312111098
RESERVEDGAN_VS7[13:0]
R/W-00bR/W-00000000000000b
76543210
GAN_VS7[13:0]
R/W-00000000000000b
Table 6-90 GAN_VS7 Register Field Descriptions
BitFieldTypeResetDescription
15:14RESERVEDR/W00bReserved. Do not change from the default reset value.
13:0GAN_VS7[13:0]R/W00000000000000bGain correction register for VS7.
The gain correction value is in two's complement representation, and is done after offset operation. During gain operation, the conversion data are multiplied by (1 + GAN_VSn[13:0] / 10000h).

6.6.3.16 GAN_VS6 Register (Address = 0x1B) [Reset = 0x0000]

Return to the Summary Table.

Figure 6-85 GAN_VS6 Register
15141312111098
RESERVEDGAN_VS6[13:0]
R/W-00bR/W-00000000000000b
76543210
GAN_VS6[13:0]
R/W-00000000000000b
Table 6-91 GAN_VS6 Register Field Descriptions
BitFieldTypeResetDescription
15:14RESERVEDR/W00bReserved. Do not change from the default reset value.
13:0GAN_VS6[13:0]R/W00000000000000bGain correction register for VS6.
The gain correction value is in two's complement representation, and is done after offset operation. During gain operation, the conversion data are multiplied by (1 + GAN_VSn[13:0] / 10000h).

6.6.3.17 GAN_VS5 Register (Address = 0x1C) [Reset = 0x0000]

Return to the Summary Table.

Figure 6-86 GAN_VS5 Register
15141312111098
RESERVEDGAN_VS5[13:0]
R/W-00bR/W-00000000000000b
76543210
GAN_VS5[13:0]
R/W-00000000000000b
Table 6-92 GAN_VS5 Register Field Descriptions
BitFieldTypeResetDescription
15:14RESERVEDR/W00bReserved. Do not change from the default reset value.
13:0GAN_VS5[13:0]R/W00000000000000bGain correction register for VS5.
The gain correction value is in two's complement representation, and is done after offset operation. During gain operation, the conversion data are multiplied by (1 + GAN_VSn[13:0] / 10000h).

6.6.3.18 GAN_VS4 Register (Address = 0x1D) [Reset = 0x0000]

Return to the Summary Table.

Figure 6-87 GAN_VS4 Register
15141312111098
RESERVEDGAN_VS4[13:0]
R/W-00bR/W-00000000000000b
76543210
GAN_VS4[13:0]
R/W-00000000000000b
Table 6-93 GAN_VS4 Register Field Descriptions
BitFieldTypeResetDescription
15:14RESERVEDR/W00bReserved. Do not change from the default reset value.
13:0GAN_VS4[13:0]R/W00000000000000bGain correction register for VS4.
The gain correction value is in two's complement representation, and is done after offset operation. During gain operation, the conversion data are multiplied by (1 + GAN_VSn[13:0] / 10000h).

6.6.3.19 GAN_VS3 Register (Address = 0x1E) [Reset = 0x0000]

Return to the Summary Table.

Figure 6-88 GAN_VS3 Register
15141312111098
RESERVEDGAN_VS3[13:0]
R/W-00bR/W-00000000000000b
76543210
GAN_VS3[13:0]
R/W-00000000000000b
Table 6-94 GAN_VS3 Register Field Descriptions
BitFieldTypeResetDescription
15:14RESERVEDR/W00bReserved. Do not change from the default reset value.
13:0GAN_VS3[13:0]R/W00000000000000bGain correction register for VS3.
The gain correction value is in two's complement representation, and is done after offset operation. During gain operation, the conversion data are multiplied by (1 + GAN_VSn[13:0] / 10000h).

6.6.3.20 GAN_VS2 Register (Address = 0x1F) [Reset = 0x0000]

Return to the Summary Table.

Figure 6-89 GAN_VS2 Register
15141312111098
RESERVEDGAN_VS2[13:0]
R/W-00bR/W-00000000000000b
76543210
GAN_VS2[13:0]
R/W-00000000000000b
Table 6-95 GAN_VS2 Register Field Descriptions
BitFieldTypeResetDescription
15:14RESERVEDR/W00bReserved. Do not change from the default reset value.
13:0GAN_VS2[13:0]R/W00000000000000bGain correction register for VS2.
The gain correction value is in two's complement representation, and is done after offset operation. During gain operation, the conversion data are multiplied by (1 + GAN_VSn[13:0] / 10000h).

6.6.3.21 GAN_VS1 Register (Address = 0x20) [Reset = 0x0000]

Return to the Summary Table.

Figure 6-90 GAN_VS1 Register
15141312111098
RESERVEDGAN_VS1[13:0]
R/W-00bR/W-00000000000000b
76543210
GAN_VS1[13:0]
R/W-00000000000000b
Table 6-96 GAN_VS1 Register Field Descriptions
BitFieldTypeResetDescription
15:14RESERVEDR/W00bReserved. Do not change from the default reset value.
13:0GAN_VS1[13:0]R/W00000000000000bGain correction register for VS1.
The gain correction value is in two's complement representation, and is done after offset operation. During gain operation, the conversion data are multiplied by (1 + GAN_VSn[13:0] / 10000h).

6.6.3.22 DWC_CFG Register (Address = 0x21) [Reset = 0x0000]

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Figure 6-91 DWC_CFG Register
15141312111098
DWC_RSTRESERVEDDWC_GLITCH_FILT[3:0]
R/W-0bR/W-000bR/W-0000b
76543210
DWC_EN_VS1DWC_EN_VS2DWC_EN_VS3DWC_EN_VS4DWC_EN_VS5DWC_EN_VS6DWC_EN_VS7DWC_EN_VS8
R/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0b
Table 6-97 DWC_CFG Register Field Descriptions
BitFieldTypeResetDescription
15DWC_RSTR/W0bDigital window comparator reset control. Write 1'b to reset.
14:12RESERVEDR/W000bReserved. Do not change from the default reset value.
11:8DWC_GLITCH_FILT[3:0]R/W0000bDigital window comparator glitch rejection filter control.
Comparator flag is set only when ADC data exceeds the threshold for consecutive number of DWC_GLITCH_FILT[3:0] cycles.
7DWC_EN_VS1R/W0bDigital window comparator enable.
  • 0b = Disabled
  • 1b = Enabled
6DWC_EN_VS2R/W0bDigital window comparator enable.
  • 0b = Disabled
  • 1b = Enabled
5DWC_EN_VS3R/W0bDigital window comparator enable.
  • 0b = Disabled
  • 1b = Enabled
4DWC_EN_VS4R/W0bDigital window comparator enable.
  • 0b = Disabled
  • 1b = Enabled
3DWC_EN_VS5R/W0bDigital window comparator enable.
  • 0b = Disabled
  • 1b = Enabled
2DWC_EN_VS6R/W0bDigital window comparator enable.
  • 0b = Disabled
  • 1b = Enabled
1DWC_EN_VS7R/W0bDigital window comparator enable.
  • 0b = Disabled
  • 1b = Enabled
0DWC_EN_VS8R/W0bDigital window comparator enable.
  • 0b = Disabled
  • 1b = Enabled

6.6.3.23 DWC_TH_VS8 Register (Address = 0x22) [Reset = 0xFF00]

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Figure 6-92 DWC_TH_VS8 Register
15141312111098
HIGH_TH_VS8[7:0]
R/W-11111111b
76543210
LOW_TH_VS8[7:0]
R/W-00000000b
Table 6-98 DWC_TH_VS8 Register Field Descriptions
BitFieldTypeResetDescription
15:8HIGH_TH_VS8[7:0]R/W11111111bMSB aligned high threshold for analog input. These bits are compared with top 8 bits of ADC conversion result.
7:0LOW_TH_VS8[7:0]R/W00000000bMSB aligned low threshold for analog input. These bits are compared with top 8 bits of ADC conversion result.

6.6.3.24 DWC_TH_VS7 Register (Address = 0x23) [Reset = 0xFF00]

Return to the Summary Table.

Figure 6-93 DWC_TH_VS7 Register
15141312111098
HIGH_TH_VS7[7:0]
R/W-11111111b
76543210
LOW_TH_VS7[7:0]
R/W-00000000b
Table 6-99 DWC_TH_VS7 Register Field Descriptions
BitFieldTypeResetDescription
15:8HIGH_TH_VS7[7:0]R/W11111111bMSB aligned high threshold for analog input. These bits are compared with top 8 bits of ADC conversion result.
7:0LOW_TH_VS7[7:0]R/W00000000bMSB aligned low threshold for analog input. These bits are compared with top 8 bits of ADC conversion result.

6.6.3.25 DWC_TH_VS6 Register (Address = 0x24) [Reset = 0xFF00]

Return to the Summary Table.

Figure 6-94 DWC_TH_VS6 Register
15141312111098
HIGH_TH_VS6[7:0]
R/W-11111111b
76543210
LOW_TH_VS6[7:0]
R/W-00000000b
Table 6-100 DWC_TH_VS6 Register Field Descriptions
BitFieldTypeResetDescription
15:8HIGH_TH_VS6[7:0]R/W11111111bMSB aligned high threshold for analog input. These bits are compared with top 8 bits of ADC conversion result.
7:0LOW_TH_VS6[7:0]R/W00000000bMSB aligned low threshold for analog input. These bits are compared with top 8 bits of ADC conversion result.

6.6.3.26 DWC_TH_VS5 Register (Address = 0x25) [Reset = 0xFF00]

Return to the Summary Table.

Figure 6-95 DWC_TH_VS5 Register
15141312111098
HIGH_TH_VS5[7:0]
R/W-11111111b
76543210
LOW_TH_VS5[7:0]
R/W-00000000b
Table 6-101 DWC_TH_VS5 Register Field Descriptions
BitFieldTypeResetDescription
15:8HIGH_TH_VS5[7:0]R/W11111111bMSB aligned high threshold for analog input. These bits are compared with top 8 bits of ADC conversion result.
7:0LOW_TH_VS5[7:0]R/W00000000bMSB aligned low threshold for analog input. These bits are compared with top 8 bits of ADC conversion result.

6.6.3.27 DWC_TH_VS4 Register (Address = 0x26) [Reset = 0xFF00]

Return to the Summary Table.

Figure 6-96 DWC_TH_VS4 Register
15141312111098
HIGH_TH_VS4[7:0]
R/W-11111111b
76543210
LOW_TH_VS4[7:0]
R/W-00000000b
Table 6-102 DWC_TH_VS4 Register Field Descriptions
BitFieldTypeResetDescription
15:8HIGH_TH_VS4[7:0]R/W11111111bMSB aligned high threshold for analog input. These bits are compared with top 8 bits of ADC conversion result.
7:0LOW_TH_VS4[7:0]R/W00000000bMSB aligned low threshold for analog input. These bits are compared with top 8 bits of ADC conversion result.

6.6.3.28 DWC_TH_VS3 Register (Address = 0x27) [Reset = 0xFF00]

Return to the Summary Table.

Figure 6-97 DWC_TH_VS3 Register
15141312111098
HIGH_TH_VS3[7:0]
R/W-11111111b
76543210
LOW_TH_VS3[7:0]
R/W-00000000b
Table 6-103 DWC_TH_VS3 Register Field Descriptions
BitFieldTypeResetDescription
15:8HIGH_TH_VS3[7:0]R/W11111111bMSB aligned high threshold for analog input. These bits are compared with top 8 bits of ADC conversion result.
7:0LOW_TH_VS3[7:0]R/W00000000bMSB aligned low threshold for analog input. These bits are compared with top 8 bits of ADC conversion result.

6.6.3.29 DWC_TH_VS2 Register (Address = 0x28) [Reset = 0xFF00]

Return to the Summary Table.

Figure 6-98 DWC_TH_VS2 Register
15141312111098
HIGH_TH_VS2[7:0]
R/W-11111111b
76543210
LOW_TH_VS2[7:0]
R/W-00000000b
Table 6-104 DWC_TH_VS2 Register Field Descriptions
BitFieldTypeResetDescription
15:8HIGH_TH_VS2[7:0]R/W11111111bMSB aligned high threshold for analog input. These bits are compared with top 8 bits of ADC conversion result.
7:0LOW_TH_VS2[7:0]R/W00000000bMSB aligned low threshold for analog input. These bits are compared with top 8 bits of ADC conversion result.

6.6.3.30 DWC_TH_VS1 Register (Address = 0x29) [Reset = 0xFF00]

Return to the Summary Table.

Figure 6-99 DWC_TH_VS1 Register
15141312111098
HIGH_TH_VS1[7:0]
R/W-11111111b
76543210
LOW_TH_VS1[7:0]
R/W-00000000b
Table 6-105 DWC_TH_VS1 Register Field Descriptions
BitFieldTypeResetDescription
15:8HIGH_TH_VS1[7:0]R/W11111111bMSB aligned high threshold for analog input. These bits are compared with top 8 bits of ADC conversion result.
7:0LOW_TH_VS1[7:0]R/W00000000bMSB aligned low threshold for analog input. These bits are compared with top 8 bits of ADC conversion result.

6.6.3.31 DWC_HYS_VS7_8 Register (Address = 0x2A) [Reset = 0x0000]

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Figure 6-100 DWC_HYS_VS7_8 Register
15141312111098
HYS_VS8[7:0]
R/W-00000000b
76543210
HYS_VS7[7:0]
R/W-00000000b
Table 6-106 DWC_HYS_VS7_8 Register Field Descriptions
BitFieldTypeResetDescription
15:8HYS_VS8[7:0]R/W00000000b8-bit hysteresis for high and low thresholds.
7:0HYS_VS7[7:0]R/W00000000b8-bit hysteresis for high and low thresholds.

6.6.3.32 DWC_HYS_VS5_6 Register (Address = 0x2B) [Reset = 0xFF00]

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Figure 6-101 DWC_HYS_VS5_6 Register
15141312111098
HYS_VS6[7:0]
R/W-11111111b
76543210
HYS_VS5[7:0]
R/W-00000000b
Table 6-107 DWC_HYS_VS5_6 Register Field Descriptions
BitFieldTypeResetDescription
15:8HYS_VS6[7:0]R/W11111111b8-bit hysteresis for high and low thresholds.
7:0HYS_VS5[7:0]R/W00000000b8-bit hysteresis for high and low thresholds.

6.6.3.33 DWC_HYS_VS3_4 Register (Address = 0x2C) [Reset = 0xFF00]

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Figure 6-102 DWC_HYS_VS3_4 Register
15141312111098
HYS_VS4[7:0]
R/W-11111111b
76543210
HYS_VS3[7:0]
R/W-00000000b
Table 6-108 DWC_HYS_VS3_4 Register Field Descriptions
BitFieldTypeResetDescription
15:8HYS_VS4[7:0]R/W11111111b8-bit hysteresis for high and low thresholds.
7:0HYS_VS3[7:0]R/W00000000b8-bit hysteresis for high and low thresholds.

6.6.3.34 DWC_HYS_VS1_2 Register (Address = 0x2D) [Reset = 0xFF00]

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Figure 6-103 DWC_HYS_VS1_2 Register
15141312111098
HYS_VS2[7:0]
R/W-11111111b
76543210
HYS_VS1[7:0]
R/W-00000000b
Table 6-109 DWC_HYS_VS1_2 Register Field Descriptions
BitFieldTypeResetDescription
15:8HYS_VS2[7:0]R/W11111111b8-bit hysteresis for high and low thresholds.
7:0HYS_VS1[7:0]R/W00000000b8-bit hysteresis for high and low thresholds.

6.6.3.35 TP_CFG Register (Address = 0x2E) [Reset = 0x0000]

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Figure 6-104 TP_CFG Register
15141312111098
RESERVED
R/W-000000000b
76543210
RESERVEDTP_MODE[2:0]RESERVEDTP_DIS_IDXTP_UP_DN_ENTP_EN
R/W-000000000bR/W-000bR/W-0bR/W-0bR/W-0bR/W-0b
Table 6-110 TP_CFG Register Field Descriptions
BitFieldTypeResetDescription
15:7RESERVEDR/W000000000bReserved. Do not change from the default reset value.
6:4TP_MODE[2:0]R/W000bTest pattern mode selection.
  • 000b = Constant pattern
  • 001b = Reserved
  • 010b = Ramp pattern
  • 011b = Reserved
  • 100b = Reserved
  • 101b = Reserved
3RESERVEDR/W0bReserved. Do not change from the default reset value.
2TP_DIS_IDXR/W0bWhen set to 1b, channel index insertion in test pattern is disabled.
1TP_UP_DN_ENR/W0bTest pattern increment mode.
  • 0b = Increment happens at channel frame boundary.
  • 1b = Increment happens at every CONVST.
0TP_ENR/W0bTest pattern enable for VS1 to VS8.
  • 0b = ADC conversion result is launched on the data interface
  • 1b = Digital test pattern is launched on the data interface

6.6.3.36 TP_VS8 Register (Address = 0x2F) [Reset = 0x0000]

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Figure 6-105 TP_VS8 Register
15141312111098
TP_VS8[15:0]
R/W-0000000000000000b
76543210
TP_VS8[15:0]
R/W-0000000000000000b
Table 6-111 TP_VS8 Register Field Descriptions
BitFieldTypeResetDescription
15:0TP_VS8[15:0]R/W0000000000000000bFixed 16 bit pattern for VS8.

6.6.3.37 TP_VS7 Register (Address = 0x30) [Reset = 0x0000]

Return to the Summary Table.

Figure 6-106 TP_VS7 Register
15141312111098
TP_VS7[15:0]
R/W-0000000000000000b
76543210
TP_VS7[15:0]
R/W-0000000000000000b
Table 6-112 TP_VS7 Register Field Descriptions
BitFieldTypeResetDescription
15:0TP_VS7[15:0]R/W0000000000000000bFixed 16 bit pattern for VS7.

6.6.3.38 TP_VS6 Register (Address = 0x31) [Reset = 0x0000]

Return to the Summary Table.

Figure 6-107 TP_VS6 Register
15141312111098
TP_VS6[15:0]
R/W-0000000000000000b
76543210
TP_VS6[15:0]
R/W-0000000000000000b
Table 6-113 TP_VS6 Register Field Descriptions
BitFieldTypeResetDescription
15:0TP_VS6[15:0]R/W0000000000000000bFixed 16 bit pattern for VS6.

6.6.3.39 TP_VS5 Register (Address = 0x32) [Reset = 0x0000]

Return to the Summary Table.

Figure 6-108 TP_VS5 Register
15141312111098
TP_VS5[15:0]
R/W-0000000000000000b
76543210
TP_VS5[15:0]
R/W-0000000000000000b
Table 6-114 TP_VS5 Register Field Descriptions
BitFieldTypeResetDescription
15:0TP_VS5[15:0]R/W0000000000000000bFixed 16 bit pattern for VS5.

6.6.3.40 TP_VS4 Register (Address = 0x33) [Reset = 0x0000]

Return to the Summary Table.

Figure 6-109 TP_VS4 Register
15141312111098
TP_VS4[15:0]
R/W-0000000000000000b
76543210
TP_VS4[15:0]
R/W-0000000000000000b
Table 6-115 TP_VS4 Register Field Descriptions
BitFieldTypeResetDescription
15:0TP_VS4[15:0]R/W0000000000000000bFixed 16 bit pattern for VS4.

6.6.3.41 TP_VS3 Register (Address = 0x34) [Reset = 0x0000]

Return to the Summary Table.

Figure 6-110 TP_VS3 Register
15141312111098
TP_VS3[15:0]
R/W-0000000000000000b
76543210
TP_VS3[15:0]
R/W-0000000000000000b
Table 6-116 TP_VS3 Register Field Descriptions
BitFieldTypeResetDescription
15:0TP_VS3[15:0]R/W0000000000000000bFixed 16 bit pattern for VS3.

6.6.3.42 TP_VS2 Register (Address = 0x35) [Reset = 0x0000]

Return to the Summary Table.

Figure 6-111 TP_VS2 Register
15141312111098
TP_VS2[15:0]
R/W-0000000000000000b
76543210
TP_VS2[15:0]
R/W-0000000000000000b
Table 6-117 TP_VS2 Register Field Descriptions
BitFieldTypeResetDescription
15:0TP_VS2[15:0]R/W0000000000000000bFixed 16 bit pattern for VS2.

6.6.3.43 TP_VS1 Register (Address = 0x36) [Reset = 0x0000]

Return to the Summary Table.

Figure 6-112 TP_VS1 Register
15141312111098
TP_VS1[15:0]
R/W-0000000000000000b
76543210
TP_VS1[15:0]
R/W-0000000000000000b
Table 6-118 TP_VS1 Register Field Descriptions
BitFieldTypeResetDescription
15:0TP_VS1[15:0]R/W0000000000000000bFixed 16 bit pattern for VS1.

6.6.3.44 GEN_CFG1 Register (Address = 0x37) [Reset = 0x0000]

Return to the Summary Table.

Figure 6-113 GEN_CFG1 Register
15141312111098
RESERVED
R/W-00000000000000b
76543210
RESERVEDOFS_CORR_ENGAN_CORR_EN
R/W-00000000000000bR/W-0bR/W-0b
Table 6-119 GEN_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
15:2RESERVEDR/W00000000000000bReserved. Do not change from the default reset value.
1OFS_CORR_ENR/W0bOffset correction enable for VS 1 to VS8.
  • 0b = Disabled
  • 1b = Enabled
0GAN_CORR_ENR/W0bGain correction enable for VS 1 to VS8.
  • 0b = Disabled
  • 1b = Enabled

6.6.3.45 DWC_FLAG_VS1_8 Register (Address = 0x3E) [Reset = 0x0000]

Return to the Summary Table.

Figure 6-114 DWC_FLAG_VS1_8 Register
15141312111098
HIGH_FLAG_VS1HIGH_FLAG_VS2HIGH_FLAG_VS3HIGH_FLAG_VS4HIGH_FLAG_VS5HIGH_FLAG_VS6HIGH_FLAG_VS7HIGH_FLAG_VS8
R-0bR-0bR-0bR-0bR-0bR-0bR-0bR-0b
76543210
LOW_FLAG_VS1LOW_FLAG_VS2LOW_FLAG_VS3LOW_FLAG_VS4LOW_FLAG_VS5LOW_FLAG_VS6LOW_FLAG_VS7LOW_FLAG_VS8
R-0bR-0bR-0bR-0bR-0bR-0bR-0bR-0b
Table 6-120 DWC_FLAG_VS1_8 Register Field Descriptions
BitFieldTypeResetDescription
15HIGH_FLAG_VS1R0bDigital window comparator high flag for VS1.
14HIGH_FLAG_VS2R0bDigital window comparator high flag for VS2.
13HIGH_FLAG_VS3R0bDigital window comparator high flag for VS3.
12HIGH_FLAG_VS4R0bDigital window comparator high flag for VS4.
11HIGH_FLAG_VS5R0bDigital window comparator high flag for VS5.
10HIGH_FLAG_VS6R0bDigital window comparator high flag for VS6.
9HIGH_FLAG_VS7R0bDigital window comparator high flag for VS7.
8HIGH_FLAG_VS8R0bDigital window comparator high flag for VS8.
7LOW_FLAG_VS1R0bDigital window comparator low flag for VS1.
6LOW_FLAG_VS2R0bDigital window comparator low flag for VS2.
5LOW_FLAG_VS3R0bDigital window comparator low flag for VS3.
4LOW_FLAG_VS4R0bDigital window comparator low flag for VS4.
3LOW_FLAG_VS5R0bDigital window comparator low flag for VS5.
2LOW_FLAG_VS6R0bDigital window comparator low flag for VS6.
1LOW_FLAG_VS7R0bDigital window comparator low flag for VS7.
0LOW_FLAG_VS8R0bDigital window comparator low flag for VS8.