SBASB93 June   2026 ADS9308V8I

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Current Sense Programmable Gain Amplifier
      2. 6.3.2 Voltage Sense Programmable Gain Amplifier (VPGA)
      3. 6.3.3 ADC Transfer Function
      4. 6.3.4 Reference
      5. 6.3.5 Digital Averaging Filter
      6. 6.3.6 Data Interface
        1. 6.3.6.1 ADC Channel Modes
    4. 6.4 Device Functional Modes
      1. 6.4.1 Reset
      2. 6.4.2 Normal Operation
      3. 6.4.3 Standby Mode
    5. 6.5 Programming
      1. 6.5.1 Register Write Operation
      2. 6.5.2 Register Read Operation
      3. 6.5.3 Initialization Sequence
    6. 6.6 Register Maps
      1. 6.6.1 ADS93x8V8I Common Registers
      2. 6.6.2 IS1 - IS8 Channel Registers
      3. 6.6.3 VS1 - VS8 Channel Registers
  8. 7 Application and Implementation
    1. 7.1 Typical Application
      1. 7.1.1 Multichannel Lithium-ion cell formation and test
    2. 7.2 Power Supply Recommendations
    3. 7.3 Layout
      1. 7.3.1 Layout Guidelines
      2. 7.3.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Tape and Reel Information
    2. 10.2 Mechanical Data

6.3.2 Voltage Sense Programmable Gain Amplifier (VPGA)

The ADS9308V8I features voltage sense programmable amplifiers. The PGA supports both single-ended and differential inputs with a bipolar signal swing. In differential-input mode, the voltage sense PGA can take maximum common mode voltage of ±12.5V. In signal-ended mode, the maximum common mode voltage supported is ±(RANGE / 2). Table 6-2 lists the supported analog input ranges. Configure the analog input range independently for each channel with the INPUT_RANGE_VSn[2:0] register fields in PGA_CONFIG_AINx registers.

Table 6-2 Analog Input Ranges
INPUT TYPE RANGE INPUT_RANGE_VSn CM_RANGE_VSn
Single-ended ±50V 6 5
Single-ended ±25V 1 5
Single-ended ±12.5V 5 5
Single-ended ±10V 4 5
Single-ended ±6.25V 3 5
Single-ended ±5V 0 5
Single-ended ±2.5V 2 5
Differential ±25V 1 0
Differential ±12.5V 5 0
Differential ±10V 4 0
Differential ±6.25V 3 0
Differential ±5V 0 0
Differential ±2.5V 2 0
Single-ended open wire safe ±12.5V 5 6
Single-ended open wire safe ±10V 4 6
Single-ended open wire safe ±6.25V 3 6
Single-ended open wire safe ±5V 0 6
Single-ended open wire safe ±2.5V 2 6

Each voltage sense channel features an anti-aliasing, low-pass filter (LPF) at the output of the PGA. Table 6-3 lists the various programmable LPF options available in the ADS9308V8I, corresponding to the analog input range. The following illustrates the frequency responses for low-bandwidth and wide-bandwidth LPF configurations. Select the analog input bandwidth for the each analog input channels with the PGA_SEL bit field in the PGA_BW_SEL_AINn registers. By default, the all PGA are in low-bandwidth mode.

Table 6-3 Voltage Sense, Low-Pass Filter Corner Frequency
LPF PGA_BW_SEL_AINn ANALOG INPUT RANGE CORNER FREQUENCY (–3dB)
Low-bandwidth 0 All input ranges 25.5kHz
Wide-bandwidth 1 ±2.5V 280kHz
±5V 325kHz
±6.25V 300kHz
±10V, ±12.5V 350kHz
±25V, ±50V 400kHz