SBASB93 June   2026 ADS9308V8I

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Current Sense Programmable Gain Amplifier
      2. 6.3.2 Voltage Sense Programmable Gain Amplifier (VPGA)
      3. 6.3.3 ADC Transfer Function
      4. 6.3.4 Reference
      5. 6.3.5 Digital Averaging Filter
      6. 6.3.6 Data Interface
        1. 6.3.6.1 ADC Channel Modes
    4. 6.4 Device Functional Modes
      1. 6.4.1 Reset
      2. 6.4.2 Normal Operation
      3. 6.4.3 Standby Mode
    5. 6.5 Programming
      1. 6.5.1 Register Write Operation
      2. 6.5.2 Register Read Operation
      3. 6.5.3 Initialization Sequence
    6. 6.6 Register Maps
      1. 6.6.1 ADS93x8V8I Common Registers
      2. 6.6.2 IS1 - IS8 Channel Registers
      3. 6.6.3 VS1 - VS8 Channel Registers
  8. 7 Application and Implementation
    1. 7.1 Typical Application
      1. 7.1.1 Multichannel Lithium-ion cell formation and test
    2. 7.2 Power Supply Recommendations
    3. 7.3 Layout
      1. 7.3.1 Layout Guidelines
      2. 7.3.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Tape and Reel Information
    2. 10.2 Mechanical Data

6.6.2 IS1 - IS8 Channel Registers

Table 6-74 lists the memory-mapped registers for the IS1 - IS8 Channel registers. All register offset addresses not listed in Table 6-74 should be considered as reserved locations and the register contents should not be modified.

Table 6-28 IS1 - IS8 Channel
AddressAcronymBit 15Bit 14Bit 13Bit 12Bit 11Bit 10Bit 9Bit 8
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
0x08PGA_CONFIG_IS1_2RESERVEDINPUT_RANGE_IS2[2:0]
RESERVEDINPUT_RANGE_IS1[2:0]
0x09PGA_CONFIG_IS3_4RESERVEDINPUT_RANGE_IS4[2:0]
RESERVEDINPUT_RANGE_IS3[2:0]
0x0APGA_CONFIG_IS5_6RESERVEDINPUT_RANGE_IS6[2:0]
RESERVEDINPUT_RANGE_IS5[2:0]
0x0BPGA_CONFIG_IS7_8RESERVEDINPUT_RANGE_IS8[2:0]
RESERVEDINPUT_RANGE_IS7[2:0]
0x11OFS_IS1RESERVEDOFS_IS1[9:0]
OFS_IS1[9:0]
0x12OFS_IS2RESERVEDOFS_IS2[9:0]
OFS_IS2[9:0]
0x13OFS_IS3RESERVEDOFS_IS3[9:0]
OFS_IS3[9:0]
0x14OFS_IS4RESERVEDOFS_IS4[9:0]
OFS_IS4[9:0]
0x15OFS_IS5RESERVEDOFS_IS5[9:0]
OFS_IS5[9:0]
0x16OFS_IS6RESERVEDOFS_IS6[9:0]
OFS_IS6[9:0]
0x17OFS_IS7RESERVEDOFS_IS7[9:0]
OFS_IS7[9:0]
0x18OFS_IS8RESERVEDOFS_IS8[9:0]
OFS_IS8[9:0]
0x19GAN_IS1RESERVEDGAN_IS1[13:0]
GAN_IS1[13:0]
0x1AGAN_IS2RESERVEDGAN_IS2[13:0]
GAN_IS2[13:0]
0x1BGAN_IS3RESERVEDGAN_IS3[13:0]
GAN_IS3[13:0]
0x1CGAN_IS4RESERVEDGAN_IS4[13:0]
GAN_IS4[13:0]
0x1DGAN_IS5RESERVEDGAN_IS5[13:0]
GAN_IS5[13:0]
0x1EGAN_IS6RESERVEDGAN_IS6[13:0]
GAN_IS6[13:0]
0x1FGAN_IS7RESERVEDGAN_IS7[13:0]
GAN_IS7[13:0]
0x20GAN_IS8RESERVEDGAN_IS8[13:0]
GAN_IS8[13:0]
0x21DWC_CFGDWC_STAT_RSTRESERVEDDWC_GLITCH_FILT[3:0]
DWC_EN_IS8DWC_EN_IS7DWC_EN_IS6DWC_EN_IS5DWC_EN_IS4DWC_EN_IS3DWC_EN_IS2DWC_EN_IS1
0x22DWC_TH_IS1HIGH_TH_IS1[7:0]
LOW_TH_IS1[7:0]
0x23DWC_TH_IS2HIGH_TH_IS2[7:0]
LOW_TH_IS2[7:0]
0x24DWC_TH_IS3HIGH_TH_IS3[7:0]
LOW_TH_IS3[7:0]
0x25DWC_TH_IS4HIGH_TH_IS4[7:0]
LOW_TH_IS4[7:0]
0x26DWC_TH_IS5HIGH_TH_IS5[7:0]
LOW_TH_IS5[7:0]
0x27DWC_TH_IS6HIGH_TH_IS6[7:0]
LOW_TH_IS6[7:0]
0x28DWC_TH_IS7HIGH_TH_IS7[7:0]
LOW_TH_IS7[7:0]
0x29DWC_TH_IS8HIGH_TH_IS8[7:0]
LOW_TH_IS8[7:0]
0x2ADWC_HYS_IS1_2HYS_IS2[7:0]
HYS_IS1[7:0]
0x2BDWC_HYS_IS3_4HYS_IS4[7:0]
HYS_IS3[7:0]
0x2CDWC_HYS_IS5_6HYS_IS6[7:0]
HYS_IS5[7:0]
0x2DDWC_HYS_IS7_8HYS_IS8[7:0]
HYS_IS7[7:0]
0x2ETP_CFGRESERVED
RESERVEDTP_MODE[2:0]RESERVEDTP_DIS_IDXTP_UP_DN_ENTP_EN
0x2FTP_IS1TP_IS1[15:0]
TP_IS1[15:0]
0x30TP_IS2TP_IS2[15:0]
TP_IS2[15:0]
0x31TP_IS3TP_IS3[15:0]
TP_IS3[15:0]
0x32TP_IS4TP_IS4[15:0]
TP_IS4[15:0]
0x33TP_IS5TP_IS5[15:0]
TP_IS5[15:0]
0x34TP_IS6TP_IS6[15:0]
TP_IS6[15:0]
0x35TP_IS7TP_IS7[15:0]
TP_IS7[15:0]
0x36TP_IS8TP_IS8[15:0]
TP_IS8[15:0]
0x37GEN_CFG1RESERVED
RESERVEDOFS_CORR_ENGAN_CORR_EN
0x3EDWC_FLAG_IS1_8HIGH_FLAG_IS8HIGH_FLAG_IS7HIGH_FLAG_IS6HIGH_FLAG_IS5HIGH_FLAG_IS4HIGH_FLAG_IS3HIGH_FLAG_IS2HIGH_FLAG_IS1
LOW_FLAG_IS8LOW_FLAG_IS7LOW_FLAG_IS6LOW_FLAG_IS5LOW_FLAG_IS4LOW_FLAG_IS3LOW_FLAG_IS2LOW_FLAG_IS1

Complex bit access types are encoded to fit into small table cells. Table 6-75 shows the codes that are used for access types in this section.

Table 6-29 IS1 - IS8 Channel Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

6.6.2.1 PGA_CONFIG_IS1_2 Register (Address = 0x08) [Reset = 0x0000]

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Figure 6-26 PGA_CONFIG_IS1_2 Register
15141312111098
RESERVEDINPUT_RANGE_IS2[2:0]
R/W-00000bR/W-000b
76543210
RESERVEDINPUT_RANGE_IS1[2:0]
R/W-00000bR/W-000b
Table 6-30 PGA_CONFIG_IS1_2 Register Field Descriptions
BitFieldTypeResetDescription
15:11RESERVEDR/W00000bReserved. Do not change from the default reset value.
10:8INPUT_RANGE_IS2[2:0]R/W000bIS2 analog input range selection.
  • 000b = ±25mV
  • 001b = ±50mV
  • 010b = ±100mV
  • 011b = ±150mV
  • 100b = ±200mV
7:3RESERVEDR/W00000bReserved. Do not change from the default reset value.
2:0INPUT_RANGE_IS1[2:0]R/W000bIS1 analog input range selection.
  • 000b = ±25mV
  • 001b = ±50mV
  • 010b = ±100mV
  • 011b = ±150mV
  • 100b = ±200mV

6.6.2.2 PGA_CONFIG_IS3_4 Register (Address = 0x09) [Reset = 0x0000]

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Figure 6-27 PGA_CONFIG_IS3_4 Register
15141312111098
RESERVEDINPUT_RANGE_IS4[2:0]
R/W-00000bR/W-000b
76543210
RESERVEDINPUT_RANGE_IS3[2:0]
R/W-00000bR/W-000b
Table 6-31 PGA_CONFIG_IS3_4 Register Field Descriptions
BitFieldTypeResetDescription
15:11RESERVEDR/W00000bReserved. Do not change from the default reset value.
10:8INPUT_RANGE_IS4[2:0]R/W000bIS4 analog input range selection.
  • 000b = ±25mV
  • 001b = ±50mV
  • 010b = ±100mV
  • 011b = ±150mV
  • 100b = ±200mV
7:3RESERVEDR/W00000bReserved. Do not change from the default reset value.
2:0INPUT_RANGE_IS3[2:0]R/W000bIS3 analog input range selection.
  • 000b = ±25mV
  • 001b = ±50mV
  • 010b = ±100mV
  • 011b = ±150mV
  • 100b = ±200mV

6.6.2.3 PGA_CONFIG_IS5_6 Register (Address = 0x0A) [Reset = 0x0000]

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Figure 6-28 PGA_CONFIG_IS5_6 Register
15141312111098
RESERVEDINPUT_RANGE_IS6[2:0]
R/W-00000bR/W-000b
76543210
RESERVEDINPUT_RANGE_IS5[2:0]
R/W-00000bR/W-000b
Table 6-32 PGA_CONFIG_IS5_6 Register Field Descriptions
BitFieldTypeResetDescription
15:11RESERVEDR/W00000bReserved. Do not change from the default reset value.
10:8INPUT_RANGE_IS6[2:0]R/W000bIS6 analog input range selection.
  • 000b = ±25mV
  • 001b = ±50mV
  • 010b = ±100mV
  • 011b = ±150mV
  • 100b = ±200mV
7:3RESERVEDR/W00000bReserved. Do not change from the default reset value.
2:0INPUT_RANGE_IS5[2:0]R/W000bIS5 analog input range selection.
  • 000b = ±25mV
  • 001b = ±50mV
  • 010b = ±100mV
  • 011b = ±150mV
  • 100b = ±200mV

6.6.2.4 PGA_CONFIG_IS7_8 Register (Address = 0x0B) [Reset = 0x0000]

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Figure 6-29 PGA_CONFIG_IS7_8 Register
15141312111098
RESERVEDINPUT_RANGE_IS8[2:0]
R/W-00000bR/W-000b
76543210
RESERVEDINPUT_RANGE_IS7[2:0]
R/W-00000bR/W-000b
Table 6-33 PGA_CONFIG_IS7_8 Register Field Descriptions
BitFieldTypeResetDescription
15:11RESERVEDR/W00000bReserved. Do not change from the default reset value.
10:8INPUT_RANGE_IS8[2:0]R/W000bIS8 analog input range selection.
  • 000b = ±25mV
  • 001b = ±50mV
  • 010b = ±100mV
  • 011b = ±150mV
  • 100b = ±200mV
7:3RESERVEDR/W00000bReserved. Do not change from the default reset value.
2:0INPUT_RANGE_IS7[2:0]R/W000bIS7 analog input range selection.
  • 000b = ±25mV
  • 001b = ±50mV
  • 010b = ±100mV
  • 011b = ±150mV
  • 100b = ±200mV

6.6.2.5 OFS_IS1 Register (Address = 0x11) [Reset = 0x0000]

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Figure 6-30 OFS_IS1 Register
15141312111098
RESERVEDOFS_IS1[9:0]
R/W-000000bR/W-0000000000b
76543210
OFS_IS1[9:0]
R/W-0000000000b
Table 6-34 OFS_IS1 Register Field Descriptions
BitFieldTypeResetDescription
15:10RESERVEDR/W000000bReserved. Do not change from the default reset value.
9:0OFS_IS1[9:0]R/W0000000000bOffset correction register for IS1.
The offset value is in two's complement representation and is added to the conversion result. The offset operation precedes the gain operation.

6.6.2.6 OFS_IS2 Register (Address = 0x12) [Reset = 0x0000]

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Figure 6-31 OFS_IS2 Register
15141312111098
RESERVEDOFS_IS2[9:0]
R/W-000000bR/W-0000000000b
76543210
OFS_IS2[9:0]
R/W-0000000000b
Table 6-35 OFS_IS2 Register Field Descriptions
BitFieldTypeResetDescription
15:10RESERVEDR/W000000bReserved. Do not change from the default reset value.
9:0OFS_IS2[9:0]R/W0000000000bOffset correction register for IS2.
The offset value is in two's complement representation and is added to the conversion result. The offset operation precedes the gain operation.

6.6.2.7 OFS_IS3 Register (Address = 0x13) [Reset = 0x0000]

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Figure 6-32 OFS_IS3 Register
15141312111098
RESERVEDOFS_IS3[9:0]
R/W-000000bR/W-0000000000b
76543210
OFS_IS3[9:0]
R/W-0000000000b
Table 6-36 OFS_IS3 Register Field Descriptions
BitFieldTypeResetDescription
15:10RESERVEDR/W000000bReserved. Do not change from the default reset value.
9:0OFS_IS3[9:0]R/W0000000000bOffset correction register for IS3.
The offset value is in two's complement representation and is added to the conversion result. The offset operation precedes the gain operation.

6.6.2.8 OFS_IS4 Register (Address = 0x14) [Reset = 0x0000]

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Figure 6-33 OFS_IS4 Register
15141312111098
RESERVEDOFS_IS4[9:0]
R/W-000000bR/W-0000000000b
76543210
OFS_IS4[9:0]
R/W-0000000000b
Table 6-37 OFS_IS4 Register Field Descriptions
BitFieldTypeResetDescription
15:10RESERVEDR/W000000bReserved. Do not change from the default reset value.
9:0OFS_IS4[9:0]R/W0000000000bOffset correction register for IS4.
The offset value is in two's complement representation and is added to the conversion result. The offset operation precedes the gain operation.

6.6.2.9 OFS_IS5 Register (Address = 0x15) [Reset = 0x0000]

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Figure 6-34 OFS_IS5 Register
15141312111098
RESERVEDOFS_IS5[9:0]
R/W-000000bR/W-0000000000b
76543210
OFS_IS5[9:0]
R/W-0000000000b
Table 6-38 OFS_IS5 Register Field Descriptions
BitFieldTypeResetDescription
15:10RESERVEDR/W000000bReserved. Do not change from the default reset value.
9:0OFS_IS5[9:0]R/W0000000000bOffset correction register for IS5.
The offset value is in two's complement representation and is added to the conversion result. The offset operation precedes the gain operation.

6.6.2.10 OFS_IS6 Register (Address = 0x16) [Reset = 0x0000]

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Figure 6-35 OFS_IS6 Register
15141312111098
RESERVEDOFS_IS6[9:0]
R/W-000000bR/W-0000000000b
76543210
OFS_IS6[9:0]
R/W-0000000000b
Table 6-39 OFS_IS6 Register Field Descriptions
BitFieldTypeResetDescription
15:10RESERVEDR/W000000bReserved. Do not change from the default reset value.
9:0OFS_IS6[9:0]R/W0000000000bOffset correction register for IS6.
The offset value is in two's complement representation and is added to the conversion result. The offset operation precedes the gain operation.

6.6.2.11 OFS_IS7 Register (Address = 0x17) [Reset = 0x0000]

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Figure 6-36 OFS_IS7 Register
15141312111098
RESERVEDOFS_IS7[9:0]
R/W-000000bR/W-0000000000b
76543210
OFS_IS7[9:0]
R/W-0000000000b
Table 6-40 OFS_IS7 Register Field Descriptions
BitFieldTypeResetDescription
15:10RESERVEDR/W000000bReserved. Do not change from the default reset value.
9:0OFS_IS7[9:0]R/W0000000000bOffset correction register for IS7.
The offset value is in two's complement representation and is added to the conversion result. The offset operation precedes the gain operation.

6.6.2.12 OFS_IS8 Register (Address = 0x18) [Reset = 0x0000]

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Figure 6-37 OFS_IS8 Register
15141312111098
RESERVEDOFS_IS8[9:0]
R/W-000000bR/W-0000000000b
76543210
OFS_IS8[9:0]
R/W-0000000000b
Table 6-41 OFS_IS8 Register Field Descriptions
BitFieldTypeResetDescription
15:10RESERVEDR/W000000bReserved. Do not change from the default reset value.
9:0OFS_IS8[9:0]R/W0000000000bOffset correction register for IS8.
The offset value is in two's complement representation and is added to the conversion result. The offset operation precedes the gain operation.

6.6.2.13 GAN_IS1 Register (Address = 0x19) [Reset = 0x0000]

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Figure 6-38 GAN_IS1 Register
15141312111098
RESERVEDGAN_IS1[13:0]
R/W-00bR/W-00000000000000b
76543210
GAN_IS1[13:0]
R/W-00000000000000b
Table 6-42 GAN_IS1 Register Field Descriptions
BitFieldTypeResetDescription
15:14RESERVEDR/W00bReserved. Do not change from the default reset value.
13:0GAN_IS1[13:0]R/W00000000000000bGain correction register for IS1.
The gain correction value is in two's complement representation, and is done after offset operation. During gain operation, the conversion data are multiplied by (1 + GAN_ISn[13:0] / 10000h).

6.6.2.14 GAN_IS2 Register (Address = 0x1A) [Reset = 0x0000]

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Figure 6-39 GAN_IS2 Register
15141312111098
RESERVEDGAN_IS2[13:0]
R/W-00bR/W-00000000000000b
76543210
GAN_IS2[13:0]
R/W-00000000000000b
Table 6-43 GAN_IS2 Register Field Descriptions
BitFieldTypeResetDescription
15:14RESERVEDR/W00bReserved. Do not change from the default reset value.
13:0GAN_IS2[13:0]R/W00000000000000bGain correction register for IS2.
The gain correction value is in two's complement representation, and is done after offset operation. During gain operation, the conversion data are multiplied by (1 + GAN_ISn[13:0] / 10000h).

6.6.2.15 GAN_IS3 Register (Address = 0x1B) [Reset = 0x0000]

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Figure 6-40 GAN_IS3 Register
15141312111098
RESERVEDGAN_IS3[13:0]
R/W-00bR/W-00000000000000b
76543210
GAN_IS3[13:0]
R/W-00000000000000b
Table 6-44 GAN_IS3 Register Field Descriptions
BitFieldTypeResetDescription
15:14RESERVEDR/W00bReserved. Do not change from the default reset value.
13:0GAN_IS3[13:0]R/W00000000000000bGain correction register for IS3.
The gain correction value is in two's complement representation, and is done after offset operation. During gain operation, the conversion data are multiplied by (1 + GAN_ISn[13:0] / 10000h).

6.6.2.16 GAN_IS4 Register (Address = 0x1C) [Reset = 0x0000]

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Figure 6-41 GAN_IS4 Register
15141312111098
RESERVEDGAN_IS4[13:0]
R/W-00bR/W-00000000000000b
76543210
GAN_IS4[13:0]
R/W-00000000000000b
Table 6-45 GAN_IS4 Register Field Descriptions
BitFieldTypeResetDescription
15:14RESERVEDR/W00bReserved. Do not change from the default reset value.
13:0GAN_IS4[13:0]R/W00000000000000bGain correction register for IS4.
The gain correction value is in two's complement representation, and is done after offset operation. During gain operation, the conversion data are multiplied by (1 + GAN_ISn[13:0] / 10000h).

6.6.2.17 GAN_IS5 Register (Address = 0x1D) [Reset = 0x0000]

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Figure 6-42 GAN_IS5 Register
15141312111098
RESERVEDGAN_IS5[13:0]
R/W-00bR/W-00000000000000b
76543210
GAN_IS5[13:0]
R/W-00000000000000b
Table 6-46 GAN_IS5 Register Field Descriptions
BitFieldTypeResetDescription
15:14RESERVEDR/W00bReserved. Do not change from the default reset value.
13:0GAN_IS5[13:0]R/W00000000000000bGain correction register for IS5.
The gain correction value is in two's complement representation, and is done after offset operation. During gain operation, the conversion data are multiplied by (1 + GAN_ISn[13:0] / 10000h).

6.6.2.18 GAN_IS6 Register (Address = 0x1E) [Reset = 0x0000]

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Figure 6-43 GAN_IS6 Register
15141312111098
RESERVEDGAN_IS6[13:0]
R/W-00bR/W-00000000000000b
76543210
GAN_IS6[13:0]
R/W-00000000000000b
Table 6-47 GAN_IS6 Register Field Descriptions
BitFieldTypeResetDescription
15:14RESERVEDR/W00bReserved. Do not change from the default reset value.
13:0GAN_IS6[13:0]R/W00000000000000bGain correction register for IS6.
The gain correction value is in two's complement representation, and is done after offset operation. During gain operation, the conversion data are multiplied by (1 + GAN_ISn[13:0] / 10000h).

6.6.2.19 GAN_IS7 Register (Address = 0x1F) [Reset = 0x0000]

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Figure 6-44 GAN_IS7 Register
15141312111098
RESERVEDGAN_IS7[13:0]
R/W-00bR/W-00000000000000b
76543210
GAN_IS7[13:0]
R/W-00000000000000b
Table 6-48 GAN_IS7 Register Field Descriptions
BitFieldTypeResetDescription
15:14RESERVEDR/W00bReserved. Do not change from the default reset value.
13:0GAN_IS7[13:0]R/W00000000000000bGain correction register for IS7.
The gain correction value is in two's complement representation, and is done after offset operation. During gain operation, the conversion data are multiplied by (1 + GAN_ISn[13:0] / 10000h).

6.6.2.20 GAN_IS8 Register (Address = 0x20) [Reset = 0x0000]

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Figure 6-45 GAN_IS8 Register
15141312111098
RESERVEDGAN_IS8[13:0]
R/W-00bR/W-00000000000000b
76543210
GAN_IS8[13:0]
R/W-00000000000000b
Table 6-49 GAN_IS8 Register Field Descriptions
BitFieldTypeResetDescription
15:14RESERVEDR/W00bReserved. Do not change from the default reset value.
13:0GAN_IS8[13:0]R/W00000000000000bGain correction register for IS8.
The gain correction value is in two's complement representation, and is done after offset operation. During gain operation, the conversion data are multiplied by (1 + GAN_ISn[13:0] / 10000h).

6.6.2.21 DWC_CFG Register (Address = 0x21) [Reset = 0x0000]

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Figure 6-46 DWC_CFG Register
15141312111098
DWC_STAT_RSTRESERVEDDWC_GLITCH_FILT[3:0]
R/W-0bR/W-000bR/W-0000b
76543210
DWC_EN_IS8DWC_EN_IS7DWC_EN_IS6DWC_EN_IS5DWC_EN_IS4DWC_EN_IS3DWC_EN_IS2DWC_EN_IS1
R/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0b
Table 6-50 DWC_CFG Register Field Descriptions
BitFieldTypeResetDescription
15DWC_STAT_RSTR/W0bDigital window comparator reset control. Write 1'b to reset.
14:12RESERVEDR/W000bReserved. Do not change from the default reset value.
11:8DWC_GLITCH_FILT[3:0]R/W0000bDigital window comparator glitch rejection filter control.
Comparator flag is set only when ADC data exceeds the threshold for consecutive number of DWC_GLITCH_FILT[3:0] cycles.
7DWC_EN_IS8R/W0bDigital window comparator enable.
  • 0b = Disabled
  • 1b = Enabled
6DWC_EN_IS7R/W0bDigital window comparator enable.
  • 0b = Disabled
  • 1b = Enabled
5DWC_EN_IS6R/W0bDigital window comparator enable.
  • 0b = Disabled
  • 1b = Enabled
4DWC_EN_IS5R/W0bDigital window comparator enable.
  • 0b = Disabled
  • 1b = Enabled
3DWC_EN_IS4R/W0bDigital window comparator enable.
  • 0b = Disabled
  • 1b = Enabled
2DWC_EN_IS3R/W0bDigital window comparator enable.
  • 0b = Disabled
  • 1b = Enabled
1DWC_EN_IS2R/W0bDigital window comparator enable.
  • 0b = Disabled
  • 1b = Enabled
0DWC_EN_IS1R/W0bDigital window comparator enable.
  • 0b = Disabled
  • 1b = Enabled

6.6.2.22 DWC_TH_IS1 Register (Address = 0x22) [Reset = 0xFF00]

Return to the Summary Table.

Figure 6-47 DWC_TH_IS1 Register
15141312111098
HIGH_TH_IS1[7:0]
R/W-11111111b
76543210
LOW_TH_IS1[7:0]
R/W-00000000b
Table 6-51 DWC_TH_IS1 Register Field Descriptions
BitFieldTypeResetDescription
15:8HIGH_TH_IS1[7:0]R/W11111111bMSB aligned high threshold for analog input. These bits are compared with top 8 bits of ADC conversion result.
7:0LOW_TH_IS1[7:0]R/W00000000bMSB aligned low threshold for analog input. These bits are compared with top 8 bits of ADC conversion result.

6.6.2.23 DWC_TH_IS2 Register (Address = 0x23) [Reset = 0xFF00]

Return to the Summary Table.

Figure 6-48 DWC_TH_IS2 Register
15141312111098
HIGH_TH_IS2[7:0]
R/W-11111111b
76543210
LOW_TH_IS2[7:0]
R/W-00000000b
Table 6-52 DWC_TH_IS2 Register Field Descriptions
BitFieldTypeResetDescription
15:8HIGH_TH_IS2[7:0]R/W11111111bMSB aligned high threshold for analog input. These bits are compared with top 8 bits of ADC conversion result.
7:0LOW_TH_IS2[7:0]R/W00000000bMSB aligned low threshold for analog input. These bits are compared with top 8 bits of ADC conversion result.

6.6.2.24 DWC_TH_IS3 Register (Address = 0x24) [Reset = 0xFF00]

Return to the Summary Table.

Figure 6-49 DWC_TH_IS3 Register
15141312111098
HIGH_TH_IS3[7:0]
R/W-11111111b
76543210
LOW_TH_IS3[7:0]
R/W-00000000b
Table 6-53 DWC_TH_IS3 Register Field Descriptions
BitFieldTypeResetDescription
15:8HIGH_TH_IS3[7:0]R/W11111111bMSB aligned high threshold for analog input. These bits are compared with top 8 bits of ADC conversion result.
7:0LOW_TH_IS3[7:0]R/W00000000bMSB aligned low threshold for analog input. These bits are compared with top 8 bits of ADC conversion result.

6.6.2.25 DWC_TH_IS4 Register (Address = 0x25) [Reset = 0xFF00]

Return to the Summary Table.

Figure 6-50 DWC_TH_IS4 Register
15141312111098
HIGH_TH_IS4[7:0]
R/W-11111111b
76543210
LOW_TH_IS4[7:0]
R/W-00000000b
Table 6-54 DWC_TH_IS4 Register Field Descriptions
BitFieldTypeResetDescription
15:8HIGH_TH_IS4[7:0]R/W11111111bMSB aligned high threshold for analog input. These bits are compared with top 8 bits of ADC conversion result.
7:0LOW_TH_IS4[7:0]R/W00000000bMSB aligned low threshold for analog input. These bits are compared with top 8 bits of ADC conversion result.

6.6.2.26 DWC_TH_IS5 Register (Address = 0x26) [Reset = 0xFF00]

Return to the Summary Table.

Figure 6-51 DWC_TH_IS5 Register
15141312111098
HIGH_TH_IS5[7:0]
R/W-11111111b
76543210
LOW_TH_IS5[7:0]
R/W-00000000b
Table 6-55 DWC_TH_IS5 Register Field Descriptions
BitFieldTypeResetDescription
15:8HIGH_TH_IS5[7:0]R/W11111111bMSB aligned high threshold for analog input. These bits are compared with top 8 bits of ADC conversion result.
7:0LOW_TH_IS5[7:0]R/W00000000bMSB aligned low threshold for analog input. These bits are compared with top 8 bits of ADC conversion result.

6.6.2.27 DWC_TH_IS6 Register (Address = 0x27) [Reset = 0xFF00]

Return to the Summary Table.

Figure 6-52 DWC_TH_IS6 Register
15141312111098
HIGH_TH_IS6[7:0]
R/W-11111111b
76543210
LOW_TH_IS6[7:0]
R/W-00000000b
Table 6-56 DWC_TH_IS6 Register Field Descriptions
BitFieldTypeResetDescription
15:8HIGH_TH_IS6[7:0]R/W11111111bMSB aligned high threshold for analog input. These bits are compared with top 8 bits of ADC conversion result.
7:0LOW_TH_IS6[7:0]R/W00000000bMSB aligned low threshold for analog input. These bits are compared with top 8 bits of ADC conversion result.

6.6.2.28 DWC_TH_IS7 Register (Address = 0x28) [Reset = 0xFF00]

Return to the Summary Table.

Figure 6-53 DWC_TH_IS7 Register
15141312111098
HIGH_TH_IS7[7:0]
R/W-11111111b
76543210
LOW_TH_IS7[7:0]
R/W-00000000b
Table 6-57 DWC_TH_IS7 Register Field Descriptions
BitFieldTypeResetDescription
15:8HIGH_TH_IS7[7:0]R/W11111111bMSB aligned high threshold for analog input. These bits are compared with top 8 bits of ADC conversion result.
7:0LOW_TH_IS7[7:0]R/W00000000bMSB aligned low threshold for analog input. These bits are compared with top 8 bits of ADC conversion result.

6.6.2.29 DWC_TH_IS8 Register (Address = 0x29) [Reset = 0xFF00]

Return to the Summary Table.

Figure 6-54 DWC_TH_IS8 Register
15141312111098
HIGH_TH_IS8[7:0]
R/W-11111111b
76543210
LOW_TH_IS8[7:0]
R/W-00000000b
Table 6-58 DWC_TH_IS8 Register Field Descriptions
BitFieldTypeResetDescription
15:8HIGH_TH_IS8[7:0]R/W11111111bMSB aligned high threshold for analog input. These bits are compared with top 8 bits of ADC conversion result.
7:0LOW_TH_IS8[7:0]R/W00000000bMSB aligned low threshold for analog input. These bits are compared with top 8 bits of ADC conversion result.

6.6.2.30 DWC_HYS_IS1_2 Register (Address = 0x2A) [Reset = 0x0000]

Return to the Summary Table.

Figure 6-55 DWC_HYS_IS1_2 Register
15141312111098
HYS_IS2[7:0]
R/W-00000000b
76543210
HYS_IS1[7:0]
R/W-00000000b
Table 6-59 DWC_HYS_IS1_2 Register Field Descriptions
BitFieldTypeResetDescription
15:8HYS_IS2[7:0]R/W00000000b8-bit hysteresis for high and low thresholds.
7:0HYS_IS1[7:0]R/W00000000b8-bit hysteresis for high and low thresholds.

6.6.2.31 DWC_HYS_IS3_4 Register (Address = 0x2B) [Reset = 0xFF00]

Return to the Summary Table.

Figure 6-56 DWC_HYS_IS3_4 Register
15141312111098
HYS_IS4[7:0]
R/W-11111111b
76543210
HYS_IS3[7:0]
R/W-00000000b
Table 6-60 DWC_HYS_IS3_4 Register Field Descriptions
BitFieldTypeResetDescription
15:8HYS_IS4[7:0]R/W11111111b8-bit hysteresis for high and low thresholds.
7:0HYS_IS3[7:0]R/W00000000b8-bit hysteresis for high and low thresholds.

6.6.2.32 DWC_HYS_IS5_6 Register (Address = 0x2C) [Reset = 0xFF00]

Return to the Summary Table.

Figure 6-57 DWC_HYS_IS5_6 Register
15141312111098
HYS_IS6[7:0]
R/W-11111111b
76543210
HYS_IS5[7:0]
R/W-00000000b
Table 6-61 DWC_HYS_IS5_6 Register Field Descriptions
BitFieldTypeResetDescription
15:8HYS_IS6[7:0]R/W11111111b8-bit hysteresis for high and low thresholds.
7:0HYS_IS5[7:0]R/W00000000b8-bit hysteresis for high and low thresholds.

6.6.2.33 DWC_HYS_IS7_8 Register (Address = 0x2D) [Reset = 0xFF00]

Return to the Summary Table.

Figure 6-58 DWC_HYS_IS7_8 Register
15141312111098
HYS_IS8[7:0]
R/W-11111111b
76543210
HYS_IS7[7:0]
R/W-00000000b
Table 6-62 DWC_HYS_IS7_8 Register Field Descriptions
BitFieldTypeResetDescription
15:8HYS_IS8[7:0]R/W11111111b8-bit hysteresis for high and low thresholds.
7:0HYS_IS7[7:0]R/W00000000b8-bit hysteresis for high and low thresholds.

6.6.2.34 TP_CFG Register (Address = 0x2E) [Reset = 0x0000]

Return to the Summary Table.

Figure 6-59 TP_CFG Register
15141312111098
RESERVED
R/W-000000000b
76543210
RESERVEDTP_MODE[2:0]RESERVEDTP_DIS_IDXTP_UP_DN_ENTP_EN
R/W-000000000bR/W-000bR/W-0bR/W-0bR/W-0bR/W-0b
Table 6-63 TP_CFG Register Field Descriptions
BitFieldTypeResetDescription
15:7RESERVEDR/W000000000bReserved. Do not change from the default reset value.
6:4TP_MODE[2:0]R/W000bTest pattern mode selection.
  • 000b = Constant pattern
  • 001b = Reserved
  • 010b = Ramp pattern
  • 011b = Reserved
  • 100b = Reserved
  • 101b = Reserved
3RESERVEDR/W0bReserved. Do not change from the default reset value.
2TP_DIS_IDXR/W0bWhen set to 1b, channel index insertion in test pattern is disabled.
1TP_UP_DN_ENR/W0bTest pattern increment mode.
  • 0b = Increment happens at channel frame boundary.
  • 1b = Increment happens at every CONVST.
0TP_ENR/W0bTest pattern enable for IS1 to IS8.
  • 0b = ADC conversion result is launched on the data interface
  • 1b = Digital test pattern is launched on the data interface

6.6.2.35 TP_IS1 Register (Address = 0x2F) [Reset = 0x0000]

Return to the Summary Table.

Figure 6-60 TP_IS1 Register
15141312111098
TP_IS1[15:0]
R/W-0000000000000000b
76543210
TP_IS1[15:0]
R/W-0000000000000000b
Table 6-64 TP_IS1 Register Field Descriptions
BitFieldTypeResetDescription
15:0TP_IS1[15:0]R/W0000000000000000bFixed 16 bit pattern for IS1.

6.6.2.36 TP_IS2 Register (Address = 0x30) [Reset = 0x0000]

Return to the Summary Table.

Figure 6-61 TP_IS2 Register
15141312111098
TP_IS2[15:0]
R/W-0000000000000000b
76543210
TP_IS2[15:0]
R/W-0000000000000000b
Table 6-65 TP_IS2 Register Field Descriptions
BitFieldTypeResetDescription
15:0TP_IS2[15:0]R/W0000000000000000bFixed 16 bit pattern for IS2.

6.6.2.37 TP_IS3 Register (Address = 0x31) [Reset = 0x0000]

Return to the Summary Table.

Figure 6-62 TP_IS3 Register
15141312111098
TP_IS3[15:0]
R/W-0000000000000000b
76543210
TP_IS3[15:0]
R/W-0000000000000000b
Table 6-66 TP_IS3 Register Field Descriptions
BitFieldTypeResetDescription
15:0TP_IS3[15:0]R/W0000000000000000bFixed 16 bit pattern for IS3.

6.6.2.38 TP_IS4 Register (Address = 0x32) [Reset = 0x0000]

Return to the Summary Table.

Figure 6-63 TP_IS4 Register
15141312111098
TP_IS4[15:0]
R/W-0000000000000000b
76543210
TP_IS4[15:0]
R/W-0000000000000000b
Table 6-67 TP_IS4 Register Field Descriptions
BitFieldTypeResetDescription
15:0TP_IS4[15:0]R/W0000000000000000bFixed 16 bit pattern for IS4.

6.6.2.39 TP_IS5 Register (Address = 0x33) [Reset = 0x0000]

Return to the Summary Table.

Figure 6-64 TP_IS5 Register
15141312111098
TP_IS5[15:0]
R/W-0000000000000000b
76543210
TP_IS5[15:0]
R/W-0000000000000000b
Table 6-68 TP_IS5 Register Field Descriptions
BitFieldTypeResetDescription
15:0TP_IS5[15:0]R/W0000000000000000bFixed 16 bit pattern for IS5.

6.6.2.40 TP_IS6 Register (Address = 0x34) [Reset = 0x0000]

Return to the Summary Table.

Figure 6-65 TP_IS6 Register
15141312111098
TP_IS6[15:0]
R/W-0000000000000000b
76543210
TP_IS6[15:0]
R/W-0000000000000000b
Table 6-69 TP_IS6 Register Field Descriptions
BitFieldTypeResetDescription
15:0TP_IS6[15:0]R/W0000000000000000bFixed 16 bit pattern for IS6.

6.6.2.41 TP_IS7 Register (Address = 0x35) [Reset = 0x0000]

Return to the Summary Table.

Figure 6-66 TP_IS7 Register
15141312111098
TP_IS7[15:0]
R/W-0000000000000000b
76543210
TP_IS7[15:0]
R/W-0000000000000000b
Table 6-70 TP_IS7 Register Field Descriptions
BitFieldTypeResetDescription
15:0TP_IS7[15:0]R/W0000000000000000bFixed 16 bit pattern for IS7.

6.6.2.42 TP_IS8 Register (Address = 0x36) [Reset = 0x0000]

Return to the Summary Table.

Figure 6-67 TP_IS8 Register
15141312111098
TP_IS8[15:0]
R/W-0000000000000000b
76543210
TP_IS8[15:0]
R/W-0000000000000000b
Table 6-71 TP_IS8 Register Field Descriptions
BitFieldTypeResetDescription
15:0TP_IS8[15:0]R/W0000000000000000bFixed 16 bit pattern for IS8.

6.6.2.43 GEN_CFG1 Register (Address = 0x37) [Reset = 0x0000]

Return to the Summary Table.

Figure 6-68 GEN_CFG1 Register
15141312111098
RESERVED
R/W-000000000000b
76543210
RESERVEDRESERVEDOFS_CORR_ENGAN_CORR_EN
R/W-000000000000bR/W-00bR/W-0bR/W-0b
Table 6-72 GEN_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
15:4RESERVEDR/W000000000000bReserved. Do not change from the default reset value.
3:2RESERVEDR/W00bReserved. Do not change from the default reset value.
1OFS_CORR_ENR/W0bOffset correction enable for IS 1 to IS8.
  • 0b = Disabled
  • 1b = Enabled
0GAN_CORR_ENR/W0bGain correction enable for IS 1 to IS8.
  • 0b = Disabled
  • 1b = Enabled

6.6.2.44 DWC_FLAG_IS1_8 Register (Address = 0x3E) [Reset = 0x0000]

Return to the Summary Table.

Figure 6-69 DWC_FLAG_IS1_8 Register
15141312111098
HIGH_FLAG_IS8HIGH_FLAG_IS7HIGH_FLAG_IS6HIGH_FLAG_IS5HIGH_FLAG_IS4HIGH_FLAG_IS3HIGH_FLAG_IS2HIGH_FLAG_IS1
R-0bR-0bR-0bR-0bR-0bR-0bR-0bR-0b
76543210
LOW_FLAG_IS8LOW_FLAG_IS7LOW_FLAG_IS6LOW_FLAG_IS5LOW_FLAG_IS4LOW_FLAG_IS3LOW_FLAG_IS2LOW_FLAG_IS1
R-0bR-0bR-0bR-0bR-0bR-0bR-0bR-0b
Table 6-73 DWC_FLAG_IS1_8 Register Field Descriptions
BitFieldTypeResetDescription
15HIGH_FLAG_IS8R0bDigital window comparator high flag for IS8.
14HIGH_FLAG_IS7R0bDigital window comparator high flag for IS7.
13HIGH_FLAG_IS6R0bDigital window comparator high flag for IS6.
12HIGH_FLAG_IS5R0bDigital window comparator high flag for IS5.
11HIGH_FLAG_IS4R0bDigital window comparator high flag for IS4.
10HIGH_FLAG_IS3R0bDigital window comparator high flag for IS3.
9HIGH_FLAG_IS2R0bDigital window comparator high flag for IS2.
8HIGH_FLAG_IS1R0bDigital window comparator high flag for IS1.
7LOW_FLAG_IS8R0bDigital window comparator low flag for IS8.
6LOW_FLAG_IS7R0bDigital window comparator low flag for IS7.
5LOW_FLAG_IS6R0bDigital window comparator low flag for IS6.
4LOW_FLAG_IS5R0bDigital window comparator low flag for IS5.
3LOW_FLAG_IS4R0bDigital window comparator low flag for IS4.
2LOW_FLAG_IS3R0bDigital window comparator low flag for IS3.
1LOW_FLAG_IS2R0bDigital window comparator low flag for IS2.
0LOW_FLAG_IS1R0bDigital window comparator low flag for IS1.