SBASB93 June   2026 ADS9308V8I

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Current Sense Programmable Gain Amplifier
      2. 6.3.2 Voltage Sense Programmable Gain Amplifier (VPGA)
      3. 6.3.3 ADC Transfer Function
      4. 6.3.4 Reference
      5. 6.3.5 Digital Averaging Filter
      6. 6.3.6 Data Interface
        1. 6.3.6.1 ADC Channel Modes
    4. 6.4 Device Functional Modes
      1. 6.4.1 Reset
      2. 6.4.2 Normal Operation
      3. 6.4.3 Standby Mode
    5. 6.5 Programming
      1. 6.5.1 Register Write Operation
      2. 6.5.2 Register Read Operation
      3. 6.5.3 Initialization Sequence
    6. 6.6 Register Maps
      1. 6.6.1 ADS93x8V8I Common Registers
      2. 6.6.2 IS1 - IS8 Channel Registers
      3. 6.6.3 VS1 - VS8 Channel Registers
  8. 7 Application and Implementation
    1. 7.1 Typical Application
      1. 7.1.1 Multichannel Lithium-ion cell formation and test
    2. 7.2 Power Supply Recommendations
    3. 7.3 Layout
      1. 7.3.1 Layout Guidelines
      2. 7.3.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Tape and Reel Information
    2. 10.2 Mechanical Data

6.6.1 ADS93x8V8I Common Registers

Table 6-74 lists the memory-mapped registers for the ADS93x8V8I Common registers. All register offset addresses not listed in Table 6-74 should be considered as reserved locations and the register contents should not be modified.

Table 6-10 ADS93x8V8I_Common
AddressAcronymBit 15Bit 14Bit 13Bit 12Bit 11Bit 10Bit 9Bit 8
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
0x01GEN_CFG1REG_RD_ADD[7:0]
RESERVEDSW_RSTREG_RD_EN
0x02BANK_SELRESERVED
RESERVEDBANK_SEL[2:0]
0x07DIAG_CTRLRESERVEDRESET_DETECT_FLAG
RESERVED
0x08PDN_CTLRESERVED
RESERVEDDEVICE_PDN
0x09GEN_CFG2RESERVEDDAISY_CHN_LOC[3:0]
DAISY_CHN_NUM[3:0]RESERVEDDAISY_CHN_EN
0x0AGEN_CFG3RESERVEDEN_OFS_BINARYRESERVEDEN_XOR_PATTEN_DIAG_FLAG
RESERVEDDOUT_LANE_SEL[1:0]DOUT_LENGTH[1:0]ADC_DATA_SDOUT_ENRESERVED
0x0BXOR_BITS_CTLRESERVED
XOR_MODE[1:0]NUM_XOR_BITS[1:0]RESERVEDXOR_BIT_SEL
0x0CDRDY_ALARM_SELALRM_MASK[7:0]
RESERVEDALRM_TYPEALRM_POLDRDY_ALRM_SEL[3:0]
0x0DGEN_CFG4RESERVED
RESERVEDALRM_DISRESERVEDDIG_DELAY_ENRESERVEDDRIVE_STRENGTH[1:0]
0x0EDIG_DELAY_CFG1RESERVEDDIG_DELAY_SDOUT[2:0]DIG_DELAY_D3[2:0]DIG_DELAY_D2[2:0]
DIG_DELAY_D2[2:0]DIG_DELAY_D1[2:0]DIG_DELAY_D0[2:0]
0x0FDIG_DELAY_CFG2RESERVEDDIG_DELAY_D7[2:0]DIG_DELAY_D6[2:0]
DIG_DELAY_D6[2:0]DIG_DELAY_D5[2:0]DIG_DELAY_D4[2:0]
0x10ANA_CFG1RESERVED
RESERVEDREFSEL_CTRL_DISEXT_REF_EN
0x11ANA_CFG2RESERVED
RESERVEDADC_CH_SEL[2:0]ADC_NUM_SEL[1:0]RESERVED
0x14DIG_FILTERRESERVED
BLK_AVG_OSR[3:0]RESERVEDDIG_FILT_SYSREF
0x15GEN_CFG5RESERVED
RESERVEDT_MODE_OVR_ENT_MODERESERVED
0x21DEVICE_IDRESERVED
DEVICE_ID[7:0]

Complex bit access types are encoded to fit into small table cells. Table 6-75 shows the codes that are used for access types in this section.

Table 6-11 ADS93x8V8I Common Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

6.6.1.1 GEN_CFG1 Register (Address = 0x01) [Reset = 0x0000]

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Figure 6-10 GEN_CFG1 Register
15141312111098
REG_RD_ADD[7:0]
R/W-00000000b
76543210
RESERVEDSW_RSTREG_RD_EN
R/W-000000bR/W-0bR/W-0b
Table 6-12 GEN_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
15:8REG_RD_ADD[7:0]R/W00000000bRegister read address
7:2RESERVEDR/W000000bReserved. Do not change from the default reset value.
1SW_RSTR/W0bWriting 1b to this bit resets the device.
0REG_RD_ENR/W0bRegister read enable

6.6.1.2 BANK_SEL Register (Address = 0x02) [Reset = 0x0001]

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Figure 6-11 BANK_SEL Register
15141312111098
RESERVED
R/W-0000000000000b
76543210
RESERVEDBANK_SEL[2:0]
R/W-0000000000000bR/W-001b
Table 6-13 BANK_SEL Register Field Descriptions
BitFieldTypeResetDescription
15:3RESERVEDR/W0000000000000bReserved. Do not change from the default reset value.
2:0BANK_SEL[2:0]R/W001bRegister bank selection.
  • 001b = Common Registers
  • 010b = IS1 - IS8 Channel Registers
  • 100b = VS1 - VS8 Channel Registers

6.6.1.3 DIAG_CTRL Register (Address = 0x07) [Reset = 0x0100]

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Figure 6-12 DIAG_CTRL Register
15141312111098
RESERVEDRESERVEDRESET_DETECT_FLAG
R/W-0bR/W-000000bR/W-1b
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-00bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0b
Table 6-14 DIAG_CTRL Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR/W0bReserved. Do not change from the default reset value.
14:9RESERVEDR/W000000bReserved. Do not change from the default reset value.
8RESET_DETECT_FLAGR/W1bIndicates reset of the device, User writes this bit to 0b. If the ADC undergoes reset, the bit is set to 1b. This bit can be read on the SDOUT status bits.
7:6RESERVEDR/W00bReserved. Do not change from the default reset value.
5RESERVEDR/W0bReserved. Do not change from the default reset value.
4RESERVEDR/W0bReserved. Do not change from the default reset value.
3RESERVEDR/W0bReserved. Do not change from the default reset value.
2RESERVEDR/W0bReserved. Do not change from the default reset value.
1RESERVEDR/W0bReserved. Do not change from the default reset value.
0RESERVEDR/W0bReserved. Do not change from the default reset value.

6.6.1.4 PDN_CTL Register (Address = 0x08) [Reset = 0x0000]

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Figure 6-13 PDN_CTL Register
15141312111098
RESERVED
R/W-000000000000000b
76543210
RESERVEDDEVICE_PDN
R/W-000000000000000bR/W-0b
Table 6-15 PDN_CTL Register Field Descriptions
BitFieldTypeResetDescription
15:1RESERVEDR/W000000000000000bReserved. Do not change from the default reset value.
0DEVICE_PDNR/W0bDevice power down control.
  • 0b = Normal operation
  • 1b = Device is in power down

6.6.1.5 GEN_CFG2 Register (Address = 0x09) [Reset = 0x0000]

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Figure 6-14 GEN_CFG2 Register
15141312111098
RESERVEDDAISY_CHN_LOC[3:0]
R/W-0000bR/W-0000b
76543210
DAISY_CHN_NUM[3:0]RESERVEDDAISY_CHN_EN
R/W-0000bR/W-000bR/W-0b
Table 6-16 GEN_CFG2 Register Field Descriptions
BitFieldTypeResetDescription
15:12RESERVEDR/W0000bReserved. Do not change from the default reset value.
11:8DAISY_CHN_LOC[3:0]R/W0000bLocation of the device in the daisy chain configuration.
7:4DAISY_CHN_NUM[3:0]R/W0000bTotal number of devices in the daisy chain configuration.
3:1RESERVEDR/W000bReserved. Do not change from the default reset value.
0DAISY_CHN_ENR/W0bDaisy chain configuration enable.
  • 0b = Daisy chain configuration disabled
  • 1b = Daisy chain configuration enabled

6.6.1.6 GEN_CFG3 Register (Address = 0x0A) [Reset = 0x0108]

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Figure 6-15 GEN_CFG3 Register
15141312111098
RESERVEDEN_OFS_BINARYRESERVEDEN_XOR_PATTEN_DIAG_FLAG
R/W-000bR/W-0bR/W-00bR/W-0bR/W-1b
76543210
RESERVEDDOUT_LANE_SEL[1:0]DOUT_LENGTH[1:0]ADC_DATA_SDOUT_ENRESERVED
R/W-00bR/W-00bR/W-10bR/W-0bR/W-0b
Table 6-17 GEN_CFG3 Register Field Descriptions
BitFieldTypeResetDescription
15:13RESERVEDR/W000bReserved. Do not change from the default reset value.
12EN_OFS_BINARYR/W0bADC conversion data output format selection.
  • 0b = Two's complement
  • 1b = Offset binary
11:10RESERVEDR/W00bReserved. Do not change from the default reset value.
9EN_XOR_PATTR/W0bEnables XOR operation on the ADC conversion result.
  • 0b = XOR operation is disabled
  • 1b = Bit-wise XOR operation on ADC conversion result is enabled
8EN_DIAG_FLAGR/W1bEnables status bits after the ADC conversion data output.
7:6RESERVEDR/W00bReserved. Do not change from the default reset value.
5:4DOUT_LANE_SEL[1:0]R/W00bData lane selection.
  • 00b = 8 lanes
  • 01b = 4 lanes
  • 10b = 2 lanes
  • 11b = 1 lane
3:2DOUT_LENGTH[1:0]R/W10bADC data size selection.
  • 00b = 16-bit
  • 01b = Reserved
  • 10b = 24-bit
1ADC_DATA_SDOUT_ENR/W0bADC data output on SDOUT pin enable in single lane mode.
  • 0b = ADC data output on D7
  • 1b = ADC data output on SDOUT pin
0RESERVEDR/W0bReserved. Do not change from the default reset value.

6.6.1.7 XOR_BITS_CTL Register (Address = 0x0B) [Reset = 0x0000]

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Figure 6-16 XOR_BITS_CTL Register
15141312111098
RESERVED
R/W-00000000b
76543210
XOR_MODE[1:0]NUM_XOR_BITS[1:0]RESERVEDXOR_BIT_SEL
R/W-00bR/W-00bR/W-000bR/W-0b
Table 6-18 XOR_BITS_CTL Register Field Descriptions
BitFieldTypeResetDescription
15:8RESERVEDR/W00000000bReserved. Do not change from the default reset value.
7:6XOR_MODE[1:0]R/W00bSet the XOR_MODE to 3.
5:4NUM_XOR_BITS[1:0]R/W00bSelect the number of XOR bits for ADC output randomizer. Set this bit field to 3.
3:1RESERVEDR/W000bReserved. Do not change from the default reset value.
0XOR_BIT_SELR/W0bSet this bit to 1b for PRBS bits.
  • 0b = PRBS

6.6.1.8 DRDY_ALARM_SEL Register (Address = 0x0C) [Reset = 0x0000]

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Figure 6-17 DRDY_ALARM_SEL Register
15141312111098
ALRM_MASK[7:0]
R/W-00000000b
76543210
RESERVEDALRM_TYPEALRM_POLDRDY_ALRM_SEL[3:0]
R/W-00bR/W-0bR/W-0bR/W-0000b
Table 6-19 DRDY_ALARM_SEL Register Field Descriptions
BitFieldTypeResetDescription
15:8ALRM_MASK[7:0]R/W00000000bAlarm mask selection. Each bit controls the mask for every alarm mode when OR'ed output of each alarm is selected on ALARM pin.
7:6RESERVEDR/W00bReserved. Do not change from the default reset value.
5ALRM_TYPER/W0bAlarm type selection. Applicable only for DWC.
  • 0b = Level based
  • 1b = Pulse based
4ALRM_POLR/W0bDRDY/ALARM polarity selection.
  • 0b = Active high
  • 1b = Active low
3:0DRDY_ALRM_SEL[3:0]R/W0000bDRDY/ALARM selection.
  • 0000b = ADC data ready flag (DRDY)
  • 0001b = DWC output
  • 0010b = Reserved
  • 0011b = Reserved
  • 0100b = Reserved
  • 0101b = Reserved
  • 0110b = Reserved
  • 0111b = Reserved
  • 1000b = OR'ed of all above flags with individual mask before ORing

6.6.1.9 GEN_CFG4 Register (Address = 0x0D) [Reset = 0x0000]

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Figure 6-18 GEN_CFG4 Register
15141312111098
RESERVED
R/W-0000000000b
76543210
RESERVEDALRM_DISRESERVEDDIG_DELAY_ENRESERVEDDRIVE_STRENGTH[1:0]
R/W-0000000000bR/W-0bR/W-0bR/W-0bR/W-0bR/W-00b
Table 6-20 GEN_CFG4 Register Field Descriptions
BitFieldTypeResetDescription
15:6RESERVEDR/W0000000000bReserved. Do not change from the default reset value.
5ALRM_DISR/W0bAlarm function disable.
  • 0b = Enabled
  • 1b = Disabled
4RESERVEDR/W0bReserved. Do not change from the default reset value.
3DIG_DELAY_ENR/W0bControl for digital delay on the output buffer path. 0b = Normal device operation. 1b = Digital delay on the output buffer path is enabled. The magnitude is controlled by DIG_DELAY_CFG1 and DIG_DELAY_CFG2.
2RESERVEDR/W0bReserved. Do not change from the default reset value.
1:0DRIVE_STRENGTH[1:0]R/W00bControl to configure the drive strength of the digital output buffer..
  • 00b = Normal device operation
  • 01b = 0.5 x drive strength
  • 10b = 2 x drive strength
  • 11b = 1.5 x drive strength

6.6.1.10 DIG_DELAY_CFG1 Register (Address = 0x0E) [Reset = 0x0000]

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Figure 6-19 DIG_DELAY_CFG1 Register
15141312111098
RESERVEDDIG_DELAY_SDOUT[2:0]DIG_DELAY_D3[2:0]DIG_DELAY_D2[2:0]
R/W-0bR/W-000bR/W-000bR/W-000b
76543210
DIG_DELAY_D2[2:0]DIG_DELAY_D1[2:0]DIG_DELAY_D0[2:0]
R/W-000bR/W-000bR/W-000b
Table 6-21 DIG_DELAY_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR/W0bReserved. Do not change from the default reset value.
14:12DIG_DELAY_SDOUT[2:0]R/W000bProgrammable digital delay on SDOUT.
  • 000b = 0ns delay
  • 001b = 1ns delay
  • 010b = 2ns delay
  • 011b = 3ns delay
  • 100b = 4ns delay
  • 101b = 5ns delay
11:9DIG_DELAY_D3[2:0]R/W000bProgrammable digital delay on D3.
  • 000b = 0ns delay
  • 001b = 1ns delay
  • 010b = 2ns delay
  • 011b = 3ns delay
  • 100b = 4ns delay
  • 101b = 5ns delay
8:6DIG_DELAY_D2[2:0]R/W000bProgrammable digital delay on D2.
  • 000b = 0ns delay
  • 001b = 1ns delay
  • 010b = 2ns delay
  • 011b = 3ns delay
  • 100b = 4ns delay
  • 101b = 5ns delay
5:3DIG_DELAY_D1[2:0]R/W000bProgrammable digital delay on D1.
  • 000b = 0ns delay
  • 001b = 1ns delay
  • 010b = 2ns delay
  • 011b = 3ns delay
  • 100b = 4ns delay
  • 101b = 5ns delay
2:0DIG_DELAY_D0[2:0]R/W000bProgrammable digital delay on D0.
  • 000b = 0ns delay
  • 001b = 1ns delay
  • 010b = 2ns delay
  • 011b = 3ns delay
  • 100b = 4ns delay
  • 101b = 5ns delay

6.6.1.11 DIG_DELAY_CFG2 Register (Address = 0x0F) [Reset = 0x0000]

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Figure 6-20 DIG_DELAY_CFG2 Register
15141312111098
RESERVEDDIG_DELAY_D7[2:0]DIG_DELAY_D6[2:0]
R/W-0000bR/W-000bR/W-000b
76543210
DIG_DELAY_D6[2:0]DIG_DELAY_D5[2:0]DIG_DELAY_D4[2:0]
R/W-000bR/W-000bR/W-000b
Table 6-22 DIG_DELAY_CFG2 Register Field Descriptions
BitFieldTypeResetDescription
15:12RESERVEDR/W0000bReserved. Do not change from the default reset value.
11:9DIG_DELAY_D7[2:0]R/W000bProgrammable digital delay on D7.
  • 000b = 0ns delay
  • 001b = 1ns delay
  • 010b = 2ns delay
  • 011b = 3ns delay
  • 100b = 4ns delay
  • 101b = 5ns delay
8:6DIG_DELAY_D6[2:0]R/W000bProgrammable digital delay on D6.
  • 000b = 0ns delay
  • 001b = 1ns delay
  • 010b = 2ns delay
  • 011b = 3ns delay
  • 100b = 4ns delay
  • 101b = 5ns delay
5:3DIG_DELAY_D5[2:0]R/W000bProgrammable digital delay on D5.
  • 000b = 0ns delay
  • 001b = 1ns delay
  • 010b = 2ns delay
  • 011b = 3ns delay
  • 100b = 4ns delay
  • 101b = 5ns delay
2:0DIG_DELAY_D4[2:0]R/W000bProgrammable digital delay on D4.
  • 000b = 0ns delay
  • 001b = 1ns delay
  • 010b = 2ns delay
  • 011b = 3ns delay
  • 100b = 4ns delay
  • 101b = 5ns delay

6.6.1.12 ANA_CFG1 Register (Address = 0x10) [Reset = 0x0000]

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Figure 6-21 ANA_CFG1 Register
15141312111098
RESERVED
R/W-00000000000000b
76543210
RESERVEDREFSEL_CTRL_DISEXT_REF_EN
R/W-00000000000000bR/W-0bR/W-0b
Table 6-23 ANA_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
15:2RESERVEDR/W00000000000000bReserved. Do not change from the default reset value.
1REFSEL_CTRL_DISR/W0bREFSEL pin control disable.
  • 0b = Enabled
  • 1b = Disabled
0EXT_REF_ENR/W0bADC reference select.
  • 0b = Internal reference
  • 1b = External reference

6.6.1.13 ANA_CFG2 Register (Address = 0x11) [Reset = 0x0000]

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Figure 6-22 ANA_CFG2 Register
15141312111098
RESERVEDRESERVED
R/W-0bR/W-00000000b
76543210
RESERVEDADC_CH_SEL[2:0]ADC_NUM_SEL[1:0]RESERVED
R/W-00000000bR/W-000bR/W-00bR/W-00b
Table 6-24 ANA_CFG2 Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR/W0bReserved. Do not change from the default reset value.
14:7RESERVEDR/W00000000bReserved. Do not change from the default reset value.
6:4ADC_CH_SEL[2:0]R/W000bSelect the ADC channels corresponding to ADC_NUM_SEL. These configurations work when ADC_NUM_SEL is not 00'b.
3:2ADC_NUM_SEL[1:0]R/W00bSelect the number of ADCs that are undergoing conversion. When ADC_NUM_SEL is 00'b, ADC_CH_SEL is don’t care.
  • 00b = 16 Channels (Default)
  • 01b = 8 Channels
  • 10b = 4 Channels
  • 11b = 2 Channels
1:0RESERVEDR/W00bReserved. Do not change from the default reset value.

6.6.1.14 DIG_FILTER Register (Address = 0x14) [Reset = 0x0000]

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Figure 6-23 DIG_FILTER Register
15141312111098
RESERVED
R/W-00000000b
76543210
BLK_AVG_OSR[3:0]RESERVEDDIG_FILT_SYSREF
R/W-0000bR/W-000bR/W-0b
Table 6-25 DIG_FILTER Register Field Descriptions
BitFieldTypeResetDescription
15:8RESERVEDR/W00000000bReserved. Do not change from the default reset value.
7:4BLK_AVG_OSR[3:0]R/W0000bOversampling ratio (OSR) configuration for block average filter. Minimum supported OSR is 8.
  • 0000b = Reserved
  • 0001b = Reserved
  • 0010b = Reserved
  • 0011b = Reserved
  • 0100b = 8 samples averaged
  • 0101b = Reserved
  • 0110b = 12 samples averaged
  • 0111b = 16 samples averaged
  • 1000b = Reserved
  • 1001b = 32 samples averaged
  • 1010b = 64 samples averaged
  • 1011b = 128 samples averaged
3:1RESERVEDR/W000bReserved. Do not change from the default reset value.
0DIG_FILT_SYSREFR/W0bWriting 1b to this bit resets the average filter at the falling edge of CONVST.

6.6.1.15 GEN_CFG5 Register (Address = 0x15) [Reset = 0x0000]

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Figure 6-24 GEN_CFG5 Register
15141312111098
RESERVED
R/W-000000000000b
76543210
RESERVEDT_MODE_OVR_ENT_MODERESERVEDRESERVED
R/W-000000000000bR/W-0bR/W-0bR/W-0bR/W-0b
Table 6-26 GEN_CFG5 Register Field Descriptions
BitFieldTypeResetDescription
15:4RESERVEDR/W000000000000bReserved. Do not change from the default reset value.
3T_MODE_OVR_ENR/W0bThis bit enables T_MODE (truncate mode feature). Set this bit to 1b before configuring the T_MODE field.
2T_MODER/W0bThis bit allows the user to truncate the ADC output to 16b when using test pattern of this device.
1RESERVEDR/W0bReserved. Do not change from the default reset value.
0RESERVEDR/W0bReserved. Do not change from the default reset value.

6.6.1.16 DEVICE_ID Register (Address = 0x21) [Reset = 0x0085]

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Figure 6-25 DEVICE_ID Register
15141312111098
RESERVED
R-00000000b
76543210
DEVICE_ID[7:0]
R-10000101b
Table 6-27 DEVICE_ID Register Field Descriptions
BitFieldTypeResetDescription
15:8RESERVEDR00000000bReserved. Do not change from the default reset value.
7:0DEVICE_ID[7:0]R10000101bDevice ID.