SBASB93 June   2026 ADS9308V8I

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Current Sense Programmable Gain Amplifier
      2. 6.3.2 Voltage Sense Programmable Gain Amplifier (VPGA)
      3. 6.3.3 ADC Transfer Function
      4. 6.3.4 Reference
      5. 6.3.5 Digital Averaging Filter
      6. 6.3.6 Data Interface
        1. 6.3.6.1 ADC Channel Modes
    4. 6.4 Device Functional Modes
      1. 6.4.1 Reset
      2. 6.4.2 Normal Operation
      3. 6.4.3 Standby Mode
    5. 6.5 Programming
      1. 6.5.1 Register Write Operation
      2. 6.5.2 Register Read Operation
      3. 6.5.3 Initialization Sequence
    6. 6.6 Register Maps
      1. 6.6.1 ADS93x8V8I Common Registers
      2. 6.6.2 IS1 - IS8 Channel Registers
      3. 6.6.3 VS1 - VS8 Channel Registers
  8. 7 Application and Implementation
    1. 7.1 Typical Application
      1. 7.1.1 Multichannel Lithium-ion cell formation and test
    2. 7.2 Power Supply Recommendations
    3. 7.3 Layout
      1. 7.3.1 Layout Guidelines
      2. 7.3.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Tape and Reel Information
    2. 10.2 Mechanical Data

5.7 Switching Characteristics

at AVDD_5V = 4.75V to 5.25V, AVDD_1V8 = 1.7V to 1.9V, IOVDD = 1.7V to 3.6V, VREF = 4.096V (internal or external), and maximum throughput (unless otherwise noted); minimum and maximum values at TA = –40°C to +125°C; typical values at TA = 25°C
PARAMETER TEST CONDITIONS MIN MAX UNIT
RESET
tPU Power-up time for device 100 ms
SERIAL INTERFACE
td_CSDO Delay time: CS falling edge to data valid on
SDOUT and D[7:0]		 16 ns
tdz_CSDO Delay time: CS rising edge to SDOUT and D[7:0] going Hi-Z 7.5 ns
tvt_CKDO Valid time: SCLK launch edge to previous
data valid on SDOUT and D[7:0]		 7.6 ns
td_CKDO Delay time: SCLK launch edge to
corresponding data valid on SDOUT and D[7:0]		 17 ns
DRDY AND ALARM
tCYC ADC cycle time period At maximum fCONVST 10 µs
tCONV Conversion time OSR = 8, and at maximum fCONVST 8 8.25 µs
OSR >= 8 (N-1) × tCONVST + 1 (N-1) × tCONVST + 1.25 µs
td_CVDRDY_hi Time delay between CONVST falling edge to DRDY rising edge tCONV ns
td_CVDRDY_lo Time delay between CONVST falling edge to DRDY falling edge 10 ns
td_ALARM Time delay between CONVST to new ALARM valid tCONV µs