SBAU249A October   2015  – July 2025 ADS9110

 

  1.   1
  2.   2
  3.   Trademarks
  4. 1Evaluation Module Overview
    1. 1.1 ADS9110EVM-PDK Features
    2. 1.2 ADS9110EVM Features
  5. 2Analog Interface
    1. 2.1 Connectors for Differential Signal Source
    2. 2.2 ADC Differential Input Signal Driver
      1. 2.2.1 Input Signal Path
      2. 2.2.2 Input Common-Mode Jumper Configuration
      3. 2.2.3 R1 Setting vs Source Impedance
    3. 2.3 Onboard ADC Reference
  6. 3Digital Interfaces
    1. 3.1 multiSPI® for ADC Digital IO
  7. 4Power Supplies
  8. 5 ADS9110EVM-PDK Initial Setup
    1. 5.1 Default Jumper Settings
    2. 5.2 EVM Graphical User Interface (GUI) Software Installation
  9. 6 ADS9110EVM-PDK Operation
    1. 6.1 EVM GUI Global Settings for ADC Control
    2. 6.2 Register Map Configuration Tool
    3. 6.3 Time Domain Display Tool
    4. 6.4 Spectral Analysis Tool
    5. 6.5 Histogram Tool
    6. 6.6 Linearity Analysis Tool
  10. 7Hardware Design Files
    1. 7.1 Schematics
    2. 7.2 PCB Layout
    3. 7.3 Bill of Materials
  11. 8Revision History

4 Power Supplies

The PHI provides multiple power-supply options for the EVM, derived from the USB supply of the computer.

The EEPROM on the ADS9110EVM use a 3.3V power supply generated directly by the PHI. The ADC and analog input drive circuits are powered by the TPS7A4700 onboard the EVM, which is a low-noise linear regulator that uses the 5.5V supply out of a switching regulator on the PHI to generate a much cleaner 5.2V output. The 1.8 V supply to the digital section of the ADC is provided directly by an LDO on the PHI.

The power supply for each active component on the EVM is bypassed with a ceramic capacitor placed close to that component. Additionally, the EVM layout uses thick traces or large copper fill areas, where possible, between bypass capacitors and the loads to minimize inductance along the load current path.