SBAU315B July   2018  – March 2025 ADS9224R , ADS9234R

 

  1.   1
  2.   ADS9224REVM-PDK
  3.   Trademarks
  4. 1Overview
    1. 1.1 ADS9224REVM-PDK Features
    2. 1.2 ADS9224REVM Features
  5. 2Analog Interface
    1. 2.1 Connectors for Signal Source
    2. 2.2 ADC Differential Input Signal Driver
      1. 2.2.1 Input Signal Path
    3. 2.3 ADS9224R Internal Reference
  6. 3Digital Interfaces
    1. 3.1 multiSPI for ADC Digital IO
  7. 4Power Supplies
  8. 5Setup
    1. 5.1 Default Jumper Settings
    2. 5.2 EVM Graphical User Interface (GUI) Software Installation
  9. 6Operation
    1. 6.1 EVM GUI Global Settings for ADC Control
    2. 6.2 Register Map Configuration Tool
    3. 6.3 Time Domain Display Tool
    4. 6.4 Spectral Analysis Tool
    5. 6.5 Histogram Tool
  10. 7ADS9224REVM Bill of Materials, PCB Layout, and Schematics
    1. 7.1 Bill of Materials
    2. 7.2 PCB Layout
    3. 7.3 Schematics
  11. 8Revision History

4 Power Supplies

The PHI controller provides multiple power-supply options for the EVM, derived from the USB supply of the computer.

The EEPROM on the ADS9224REVM use a 3.3-V power supply generated directly by the PHI. The ADC and analog input drive circuits are powered by the TPS7A4700 onboard the EVM. The TPS7A4700 is a low-noise linear regulator that uses the 5.5-V supply out of a switching regulator on the PHI to generate a much cleaner 5.0-V output. The 3.3-V supply to the digital section of the ADC is provided directly by an LDO regulator on the PHI.

The power supply for each active component on the EVM is bypassed with a ceramic capacitor placed close to that component. Additionally, the EVM layout uses thick traces or large copper fill areas, where possible, between bypass capacitors and their loads in order to minimize inductance along the load current path.

The LM7705 outputs a –230-mV option to drive the negative supply (VS–) of the fully-differential input amplifiers. This option allows the amplifier outputs to swing all the way to ground and achieve a full-scale differential signal at the ADC input. Configure JP8 in the [1-2] position to use the –230-mV supply for VS–. If the entire full-scale range is not required, VS– can be connected to GND by configuring JP8 in the [2-3] position. U8 can be disabled by uninstalling the jumper on JP7. Table 4-1 lists the relevant power supply test points on the EVM.

Table 4-1 Power-Supply Test Points
Designator Signal Description
TP17 GND EVM ground
TP18 LDO_IN_5V5 5.5-V supply from PHI EVM controller
TP19 VA 5-V analog supply
TP20 DVDD 3.3-V digital supply
TP21 VS– Negative supply for fully-differential input amplifiers