SBOS790A April 2017 – March 2025 INA233
PRODUCTION DATA
The INA233 features an I2C-compatible, 2-wire interface with an open-drain Alert output. The data transfer format is SMBus version 3.0 compliant and the device supports multiple PMBus commands that allow the device to be easily used along with PMBus version 1.3 devices.
The device that initiates a data transfer is called a controller, and the devices controlled by the controller are targets. The bus must be controlled by a controller device that generates the serial clock (SCL), controls the bus access, and generates START and STOP conditions.
To address a specific device, the controller initiates a START condition by pulling the data signal line (SDA) from a high to a low logic level when SCL is high. All targets on the bus shift in the target address byte on the rising edge of SCL, with the last bit indicating whether a read or write operation is intended. During the ninth clock pulse, the target being addressed responds to the controller by generating an Acknowledge and pulling SDA low.
Data transfer is then initiated and eight bits of data are sent, followed by an Acknowledge bit. During data transfer, SDA must remain stable when SCL is high. Any change in SDA when SCL is high is interpreted as a START or STOP condition.
After all data are transferred, the controller generates a STOP condition, indicated by pulling SDA from low to high when SCL is high. The device includes a 28ms timeout on the interface to prevent bus lockup.