Both writing and reading to the INA233 is accomplished through the use of various PMBus commands. Each PMBus command code is an address that allows read or write access to the internal registers; see the PMBus Command Support section for a complete list of supported PMBus commands and corresponding addresses. The value for the command address is the first byte transferred after the target address byte with the R/ W bit low. Every write operation to the device requires a value for the command address.

Writing to the device begins with the first byte transmitted by the controller. This byte is the target address with the R/ W bit low. The device then acknowledges receipt of a valid address. The next byte transmitted by the controller is the PMBus command address to the register that data are written to. This command address value updates the register pointer to the desired register. The next two bytes are written to the register addressed by the PMBus command. The device acknowledges receipt of each data byte. The controller can terminate data transfer by generating a START or STOP condition.

The timing structure for SEND BYTE commands is the same as WRITE WORD commands except no data packets are sent.

When reading from the device, first the device is written to with the desired PMBus command that is to return the desired value. This write is accomplished by issuing a target address byte with the R/ W bit low, followed by the PMBus command code. No additional data are required. The controller then generates a repeated START condition and sends the target address byte with the R/ W bit high to initiate the read command. The next byte is transmitted by the target and is the most significant byte of the register indicated by the register pointer. This byte is followed by an Acknowledge (ACK) from the controller; then the target transmits the least significant byte. The controller acknowledges receipt of the data byte. The controller can terminate data transfer by generating a Not-Acknowledge after receiving any data byte, or by generating a START or STOP condition. If repeated reads from the same register are desired, the register pointer bytes do not have to be continually sent; the device retains the register pointer value until the value is changed by the next write operation.

The READ BYTE format has the same timing structure as the READ WORD format except a byte of data is returned instead of a word.

Figure 6-4 shows the write operation timing diagram. Figure 6-5 shows the read operation timing diagram.

A. The value of the target address byte is determined by the settings of the A0 and A1 pins; see Table 6-2.

Figure 6-4 Timing Diagram for Write Word Format

A. The value of the target address byte is determined by the settings of the A0 and A1 pins; see Table 6-2.

B. Read data are from the previous PMBus command code.

C. An Acknowledge by the controller can also be sent.

Figure 6-5 Timing Diagram for Read Word Format

A block read is similar to the read word format in that first the device is written to with the desired PMBus command that is to return the desired value. This write is accomplished by issuing a target address byte with the R/ W bit low, followed by the PMBus command code. The controller then generates a repeated START condition and sends the target address byte with the R/ W bit high to initiate the read command. The next byte is transmitted by the target is the total number of bytes that are sent to the controller. This byte is followed by an Acknowledge (ACK) from the controller; then the target transmits the first data byte. At the end of each byte the controller sends an Acknowledge and the next byte is sent by the target. The controller can terminate data transfer by generating a Not-Acknowledge after receiving any data byte, or by generating a START or STOP condition.

Figure 6-6 shows the block read operation timing diagram. Figure 6-7 shows the timing diagram for the SMBus Alert response operation.

A. The value of the target address byte is determined by the settings of the A0 and A1 pins; see Table 6-2.

Figure 6-6 Timing Diagram for Block Read Format

A. The value of the target address byte is determined by the settings of the A0 and A1 pins; see Table 6-2.

Figure 6-7 Timing Diagram for SMBus ALERT Response