SBOU024C august 2004 – july 2023 PGA309
Figure 4-10 shows the read and write timing for the PGA309 interface to the external EEPROM when the PGA309 receives commands through the One-Wire interface (PRG pin). All manufacturer reading and writing modes are allowed when direct Two-Wire access is made to the external EEPROM. Note that full 10-bit EEPROM addressing mode is supported by the PGA309 One-Wire access to the external EEPROM through the PGA309 Two-Wire interface. A 1k-bit EEPROM minimum is needed for the PGA309 Configuration Register and 17 Lookup Table coefficients. A larger EEPROM can be used to store other configuration information such as serial number, date code, lot code, etc. In addition, note that the PGA309 SCL and SDA pins have light internal pull-up current sources to VSD (85μA typical on each pin). This is more than adequate for most applications that involve placing only the external EEPROM close to the PGA309 on the same printed circuit board (PCB). Other applications that add load and capacitance to the SDA and SCL lines may need additional external pull-up resistors to VSD to ensure rise timing requirements are met at all times. At the end of a EEPROM write cycle, there is a typical 5ms EEPROM write cycle during which the data is stored in a nonvolatile fashion internally to the EEPROM. During this time, if Two-Wire direct access is attempted, there will be no acknowledge from the EEPROM. If communicating to the external EEPROM through the PGA309 One-Wire interface, this EEPROM write cycle time is a No Communication Allowed time period.