SBOU024C august   2004  – july 2023 PGA309

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Related Documentation from Texas Instruments
    3.     If You Need Assistance
    4.     Information About Cautions and Warnings
    5.     FCC Warning
    6.     Trademarks
  3. 1Introduction
    1. 1.1  PGA309 Functional Description
    2. 1.2  Sensor Error Adjustment Range
    3. 1.3  Gain Scaling
    4. 1.4  Offset Adjustment
    5. 1.5  Voltage Reference
    6. 1.6  Sensor Excitation and Linearization
    7. 1.7  ADC for Temperature Sensing
    8. 1.8  External EEPROM and Temperature Coefficients
    9. 1.9  Fault Monitor
    10. 1.10 Over-Scale and Under-Scale Limits
    11. 1.11 Power-Up and Normal Operation
    12. 1.12 Digital Interface
    13. 1.13 Pin Configuration
  4. 2Detailed Description
    1. 2.1  Gain Scaling
      1. 2.1.1 PGA309 Transfer Function
      2. 2.1.2 Solving For Gain Settings
    2. 2.2  Offset Scaling
    3. 2.3  Zero DAC and Gain DAC Architecture
    4. 2.4  Output Amplifier
    5. 2.5  Reference Voltage
    6. 2.6  Linearization Function
      1. 2.6.1 System Definitions
      2. 2.6.2 Key Linearization Design Equations
        1. 2.6.2.1 Lin DAC Counts Conversion
      3. 2.6.3 Key Ideal Design Equations
        1. 2.6.3.1 Linearization Design
        2.       37
    7. 2.7  Temperature Measurement
      1. 2.7.1 Temp ADC Start-Convert Control
      2. 2.7.2 External Temperature Sensing with an Excitation Series Resistor
    8. 2.8  Fault Monitor
    9. 2.9  Over-Scale and Under-Scale
      1. 2.9.1 Over-Scale and Under-Scale Calculation
      2.      44
    10. 2.10 Noise and Coarse Offset Adjust
    11. 2.11 General AC Considerations
  5. 3Operating Modes
    1. 3.1 Power-On Sequence and Normal Stand-Alone Operation
    2. 3.2 EEPROM Content and Temperature Lookup Table Calculation
      1. 3.2.1 Temperature Lookup Table Calculation
        1. 3.2.1.1 Temperature Lookup Table Calculation
        2.       52
        3.       53
    3. 3.3 Checksum Error Event
    4. 3.4 Test Pin
    5. 3.5 Power-On Initial Register States
      1. 3.5.1 PGA309 Power-Up State
  6. 4Digital Interface
    1. 4.1  Description
    2. 4.2  Two-Wire Interface
      1. 4.2.1 Device Addressing
      2. 4.2.2 Two-Wire Access to PGA309
    3. 4.3  One-Wire Interface
    4. 4.4  One-Wire Interface Timeout
    5. 4.5  One-Wire Interface Timing Considerations
    6. 4.6  Two-Wire Access to External EEPROM
    7. 4.7  One-Wire Interface Initiated Two-Wire EEPROM Transactions
    8. 4.8  PGA309 Stand-Alone Mode and Two-Wire Transactions
    9. 4.9  PGA309 Two-Wire Bus Master Operation and Bus Sharing Considerations
    10. 4.10 One-Wire Operation with PRG Connected to VOUT
    11. 4.11 Four-Wire Modules and One-Wire Interface (PRG)
  7. 5Application Background
    1. 5.1 Bridge Sensors
    2. 5.2 System Scaling Options for Bridge Sensors
      1. 5.2.1 Absolute Scale
      2. 5.2.2 Ratiometric Scale
    3. 5.3 Trimming Real World Bridge Sensors for Linearity
    4. 5.4 PGA309 Calibration Procedure
  8. 6Register Descriptions
    1. 6.1 Internal Register Overview
    2. 6.2 Internal Register Map
      1. 6.2.1 Register 0: Temp ADC Output Register (Read Only, Address Pointer = 00000)
      2. 6.2.2 Register 1: Fine Offset Adjust (Zero DAC) Register (Read/Write, Address Pointer = 00001)
      3. 6.2.3 Register 2: Fine Gain Adjust (Gain DAC) Register (Read/Write, Address Pointer = 00010)
      4. 6.2.4 Register 3: Reference Control and Linearization Register (Read/Write, Address Pointer = 00011)
      5. 6.2.5 Register 4: PGA Coarse Offset Adjust and Gain Select/Output Amplifier Gain Select Register (Read/Write, Address Pointer = 00100)
      6. 6.2.6 Register 5: PGA Configuration and Over/Under-Scale Limit Register (Read/Write, Address Pointer = 00101)
      7. 6.2.7 Register 6: Temp ADC Control Register (Read/Write, Address Pointer = 00110)
      8. 6.2.8 Register 7: Output Enable Counter Control Register (Read/Write, Address Pointer = 00111)
      9. 6.2.9 Register 8: Alarm Status Register (Read Only, Address Pointer = 01000)
  9.   A External EEPROM Example
    1.     A.1 PGA309 External EEPROM Example
      1.      A.1.1 Gain and Offset Scaling for External EEPROM
      2.      94
  10.   B Detailed Block Diagram
    1.     B.1 Detailed Block Diagram
  11.   C Glossary
  12.   Revision History

2.9.1 Over-Scale and Under-Scale Calculation

Given:

Absolute Scale System—PGA309 connected to a system ADC (see Figure 2-25)
System ADC Reference: VREF ADC = 4.096V
PGA309 Reference: VREF = 4.096V (use PGA309 internal reference)
Operating Temperature Range: −40°C to +125°C
PGA309 VSA, VSD = +5V
External Fault Monitor; Trip High when Fault Detected

Find:

Recommended levels to allow for Over/Under-Scale Limits as well as Fault Detection.

  1. Over-Scale Limit
  2. Under-Scale Limit
  3. Useable Linear PGA309 Output Range
  4. System ADC Trip Points: Over-Scale, Under-Scale, Fault Detect

Solution:

  1. Analyze the worst case offset errors on the over-scale and under-scale comparators over the operating temperature range. Table 2-20 contains key electrical characteristics needed for this computation.
    Over-Scale Comparator Offset Calculation:
    Over-Scale Temperature Drift:
    −40°C to 25°C: −24.05mV = (+0.37mV/°C)(−40°C − 25°C)
    25°C to +125°C: +37.00mV = (+0.37mV/°C)(+125°C − 25°C)

    Over-Scale Offset Min and Max:
    VOS min = +6mV −24.05mV = −18.05mV
    VOS max = +114mV + 37.00mV = +151.00mV

    Under-Scale Comparator Offset Calculation:
    Under-Scale Temperature Drift:
    −40°C to 25°C: +9.75mV = (−0.15mV/°C)(−40°C − 25°C)
    25°C to +125°C: −15.00mV = (−0.15mV/°C)(+125°C − 25°C)

    Under-Scale Offset Min and Max:
    VUS min = −7mV + 9.75mV = −2.75mV
    VUS max = −93mV −15.00mV = −108mV
  2. Analyze the worst-case change in VREF over the operating temperature range.
    VREF Temperature Drift:
    −40°C to +125°C: [(+10ppm/°C)/(1e6)][+125°C − (−40°C)]VREF = +0.00165 VREF
    VREF Min and Max:
    VREF min = 4.00V – (0.00165)(4.00V) = 3.9934V
    VREF max = 4.14V + (0.00165)(4.00V) = 4.1466V
  3. Calculate the over-scale and under-scale min and max trip points over the operating temperature range for each overscale and under-scale threshold (refer to Table 2-21).
    Over-Scale (OS) Min and Max Trip Points:
    OS min = VREF min (OS ratio) + VOS min
    OS max = VREF max (OS ratio) + VOS max

    Under-Scale (US) Min and Max Trip Points:
    US min = VREF min (US ratio) + VUS max
    US max = VREF max (US ratio) + VUS min
  4. From the over-scale and under-scale min and max trip point calculations, choose the best selection that will allow for the optimum system ADC range budget (see Figure 2-26). For this example, the PGA309 is scalable for a linear output of 8% to 80.8% of the system ADC reference. In addition, we can set reasonable trip points for detecting over-scale limit, under-scale limit, and fault detect.
  5. Check that the PGA309 VOUT can support the voltage swings defined in the System ADC range budget. Table 2-22 confirms that for our example the PGA309 VOUT can meet the limiting conditions for our desired scaling.

Since the PGA309 + sensor is usually calibrated together as a system, the over-scale and under-scale limits can be measured per device at the operating temperature extremes, and the final limits adjusted as desired for optimum scaling. In a ratiometrically scaled system, the reference error will not need to be included in the over-scale and under-scale trip point calculations.