SBOU024C august   2004  – july 2023 PGA309

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Related Documentation from Texas Instruments
    3.     If You Need Assistance
    4.     Information About Cautions and Warnings
    5.     FCC Warning
    6.     Trademarks
  3. 1Introduction
    1. 1.1  PGA309 Functional Description
    2. 1.2  Sensor Error Adjustment Range
    3. 1.3  Gain Scaling
    4. 1.4  Offset Adjustment
    5. 1.5  Voltage Reference
    6. 1.6  Sensor Excitation and Linearization
    7. 1.7  ADC for Temperature Sensing
    8. 1.8  External EEPROM and Temperature Coefficients
    9. 1.9  Fault Monitor
    10. 1.10 Over-Scale and Under-Scale Limits
    11. 1.11 Power-Up and Normal Operation
    12. 1.12 Digital Interface
    13. 1.13 Pin Configuration
  4. 2Detailed Description
    1. 2.1  Gain Scaling
      1. 2.1.1 PGA309 Transfer Function
      2. 2.1.2 Solving For Gain Settings
    2. 2.2  Offset Scaling
    3. 2.3  Zero DAC and Gain DAC Architecture
    4. 2.4  Output Amplifier
    5. 2.5  Reference Voltage
    6. 2.6  Linearization Function
      1. 2.6.1 System Definitions
      2. 2.6.2 Key Linearization Design Equations
        1. 2.6.2.1 Lin DAC Counts Conversion
      3. 2.6.3 Key Ideal Design Equations
        1. 2.6.3.1 Linearization Design
        2.       37
    7. 2.7  Temperature Measurement
      1. 2.7.1 Temp ADC Start-Convert Control
      2. 2.7.2 External Temperature Sensing with an Excitation Series Resistor
    8. 2.8  Fault Monitor
    9. 2.9  Over-Scale and Under-Scale
      1. 2.9.1 Over-Scale and Under-Scale Calculation
      2.      44
    10. 2.10 Noise and Coarse Offset Adjust
    11. 2.11 General AC Considerations
  5. 3Operating Modes
    1. 3.1 Power-On Sequence and Normal Stand-Alone Operation
    2. 3.2 EEPROM Content and Temperature Lookup Table Calculation
      1. 3.2.1 Temperature Lookup Table Calculation
        1. 3.2.1.1 Temperature Lookup Table Calculation
        2.       52
        3.       53
    3. 3.3 Checksum Error Event
    4. 3.4 Test Pin
    5. 3.5 Power-On Initial Register States
      1. 3.5.1 PGA309 Power-Up State
  6. 4Digital Interface
    1. 4.1  Description
    2. 4.2  Two-Wire Interface
      1. 4.2.1 Device Addressing
      2. 4.2.2 Two-Wire Access to PGA309
    3. 4.3  One-Wire Interface
    4. 4.4  One-Wire Interface Timeout
    5. 4.5  One-Wire Interface Timing Considerations
    6. 4.6  Two-Wire Access to External EEPROM
    7. 4.7  One-Wire Interface Initiated Two-Wire EEPROM Transactions
    8. 4.8  PGA309 Stand-Alone Mode and Two-Wire Transactions
    9. 4.9  PGA309 Two-Wire Bus Master Operation and Bus Sharing Considerations
    10. 4.10 One-Wire Operation with PRG Connected to VOUT
    11. 4.11 Four-Wire Modules and One-Wire Interface (PRG)
  7. 5Application Background
    1. 5.1 Bridge Sensors
    2. 5.2 System Scaling Options for Bridge Sensors
      1. 5.2.1 Absolute Scale
      2. 5.2.2 Ratiometric Scale
    3. 5.3 Trimming Real World Bridge Sensors for Linearity
    4. 5.4 PGA309 Calibration Procedure
  8. 6Register Descriptions
    1. 6.1 Internal Register Overview
    2. 6.2 Internal Register Map
      1. 6.2.1 Register 0: Temp ADC Output Register (Read Only, Address Pointer = 00000)
      2. 6.2.2 Register 1: Fine Offset Adjust (Zero DAC) Register (Read/Write, Address Pointer = 00001)
      3. 6.2.3 Register 2: Fine Gain Adjust (Gain DAC) Register (Read/Write, Address Pointer = 00010)
      4. 6.2.4 Register 3: Reference Control and Linearization Register (Read/Write, Address Pointer = 00011)
      5. 6.2.5 Register 4: PGA Coarse Offset Adjust and Gain Select/Output Amplifier Gain Select Register (Read/Write, Address Pointer = 00100)
      6. 6.2.6 Register 5: PGA Configuration and Over/Under-Scale Limit Register (Read/Write, Address Pointer = 00101)
      7. 6.2.7 Register 6: Temp ADC Control Register (Read/Write, Address Pointer = 00110)
      8. 6.2.8 Register 7: Output Enable Counter Control Register (Read/Write, Address Pointer = 00111)
      9. 6.2.9 Register 8: Alarm Status Register (Read Only, Address Pointer = 01000)
  9.   A External EEPROM Example
    1.     A.1 PGA309 External EEPROM Example
      1.      A.1.1 Gain and Offset Scaling for External EEPROM
      2.      94
  10.   B Detailed Block Diagram
    1.     B.1 Detailed Block Diagram
  11.   C Glossary
  12.   Revision History

3.1 Power-On Sequence and Normal Stand-Alone Operation

The PGA309 internal state machine controls the operations of the part in Stand-Alone Mode, without any external digital controller. In this mode, the PGA309 performs the functions of a Two-Wire interface master to read the data from the EEPROM.

The PGA309 has power-on reset (POR) circuitry to reset the internal registers and subcircuits to their initial states. This power-on reset also occurs when the supply is detected to be too low so that the PGA309 is in a known state when the supply becomes valid again. The threshold for the POR circuit is typically 2.2V for VSA rising and 1.7V for VSA falling.

After the power supply becomes valid, the PGA309 waits for approximately 33ms and then attempts to read the configuration register data (Register 3—Register 6 bit settings) from the first part of the external EEPROM device. If the EEPROM has the proper programmed flag word (0x5449, “TI” ASCII) in address locations 0 and 1, the PGA309 will continue reading the EEPROM. Otherwise, the PGA309 will wait for 1.3 seconds before trying again. If the PGA309 detects that there was no response from the EEPROM and the TwoWire bus was in a valid idle state (SCL = ‘1’, SDA = ‘1’), then the PGA309 will wait for 1.3 seconds and try again. If the Two-Wire bus is stuck with SDA = ‘0’, the PGA309 will try to free the bus by sending extra clocks down SCL (see Chapter 4, Digital Interface, for details), and wait for 33ms before trying to read the EEPROM again. If the EEPROM configuration read is successful (including valid Checksum1 data) and either bits ADCS or CEN in Register 6 are set to ‘1’, the PGA309 will trigger the Temp ADC to measure the temperature information as configured in the configuration registers. For 16-bit resolution results, the converter takes approximately 125ms to complete a conversion. Once the conversion is complete, the PGA309 begins reading the Lookup Table from EEPROM address locations 16 and higher, to calculate the settings for the Gain and Zero DACs using the piecewise linear interpolation algorithm. The PGA309 reads the entire Lookup Table and determines if the checksum for the Lookup Table (Checksum2) is correct. Each entry in the Lookup Table requires approximately 500μs to read from the EEPROM. Once Checksum2 is determined to be valid, the calculated value for the Gain and Zero DACs is updated into their respective registers, and the Output Amplifier (VOUT) is enabled. The PGA309 then begins looping through this entire procedure, starting again with reading the configuration data from the first part of the EEPROM. This loop continues indefinitely.

Note:

For PRG Pin Connected to VOUT

During the entire initial power-on sequence, the PGA309 VOUT is disabled (high-impedance) until valid EEPROM contents are verified and an ADC conversion is complete, as described above and illustrated in Figure 3-1. In true three-wire connection (VS, GND, and VOUT with PRG pin shorted to VOUT), with OWD = ‘1’ (Register 4, bit D15), the time interval after power-up is the only opportunity that an external communications controller can initiate digital communication with the PGA309 and trigger a one second delay in the internal state machine. After VOUT is enabled no further digital communication is possible, unless power is cycled.

If the PGA309 detects that there is no EEPROM device present (that is, it does not receive an acknowledge to a slave address byte sent to the EEPROM), the PGA309 will wait for approximately one second and try again. It will continue in this loop indefinitely with VOUT disabled.

At any time, if the PGA309 is addressed through the Two-Wire or One-Wire interface with OWD = ‘0’ (Register 4, bit D15), the internal state machine aborts its cycle and initiates a 1s delay. After the 1s delay has timed out, a EEPROM read is started. The 1s delay is reset every time the PGA309 is addressed. This allows an external microcontroller to control the function of the PGA309, as long as some communication activity is addressed to the PGA309 at least once per second. VOUT will stay in the state (enabled or disabled) that it was in before the PGA309 was addressed. If full microcontroller control of the PGA309 is desired from initial power-on, then the Test pin should be brought high to enable the output after the internal PGA309 registers have been configured to their desired states.

GUID-F4715CED-1342-41C6-901C-E4F433A16173-low.gifFigure 3-1 State Machine—Power-On Sequence and Operation in Stand-Alone Mode