SBOU024C august   2004  – july 2023 PGA309

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Related Documentation from Texas Instruments
    3.     If You Need Assistance
    4.     Information About Cautions and Warnings
    5.     FCC Warning
    6.     Trademarks
  3. 1Introduction
    1. 1.1  PGA309 Functional Description
    2. 1.2  Sensor Error Adjustment Range
    3. 1.3  Gain Scaling
    4. 1.4  Offset Adjustment
    5. 1.5  Voltage Reference
    6. 1.6  Sensor Excitation and Linearization
    7. 1.7  ADC for Temperature Sensing
    8. 1.8  External EEPROM and Temperature Coefficients
    9. 1.9  Fault Monitor
    10. 1.10 Over-Scale and Under-Scale Limits
    11. 1.11 Power-Up and Normal Operation
    12. 1.12 Digital Interface
    13. 1.13 Pin Configuration
  4. 2Detailed Description
    1. 2.1  Gain Scaling
      1. 2.1.1 PGA309 Transfer Function
      2. 2.1.2 Solving For Gain Settings
    2. 2.2  Offset Scaling
    3. 2.3  Zero DAC and Gain DAC Architecture
    4. 2.4  Output Amplifier
    5. 2.5  Reference Voltage
    6. 2.6  Linearization Function
      1. 2.6.1 System Definitions
      2. 2.6.2 Key Linearization Design Equations
        1. 2.6.2.1 Lin DAC Counts Conversion
      3. 2.6.3 Key Ideal Design Equations
        1. 2.6.3.1 Linearization Design
        2.       37
    7. 2.7  Temperature Measurement
      1. 2.7.1 Temp ADC Start-Convert Control
      2. 2.7.2 External Temperature Sensing with an Excitation Series Resistor
    8. 2.8  Fault Monitor
    9. 2.9  Over-Scale and Under-Scale
      1. 2.9.1 Over-Scale and Under-Scale Calculation
      2.      44
    10. 2.10 Noise and Coarse Offset Adjust
    11. 2.11 General AC Considerations
  5. 3Operating Modes
    1. 3.1 Power-On Sequence and Normal Stand-Alone Operation
    2. 3.2 EEPROM Content and Temperature Lookup Table Calculation
      1. 3.2.1 Temperature Lookup Table Calculation
        1. 3.2.1.1 Temperature Lookup Table Calculation
        2.       52
        3.       53
    3. 3.3 Checksum Error Event
    4. 3.4 Test Pin
    5. 3.5 Power-On Initial Register States
      1. 3.5.1 PGA309 Power-Up State
  6. 4Digital Interface
    1. 4.1  Description
    2. 4.2  Two-Wire Interface
      1. 4.2.1 Device Addressing
      2. 4.2.2 Two-Wire Access to PGA309
    3. 4.3  One-Wire Interface
    4. 4.4  One-Wire Interface Timeout
    5. 4.5  One-Wire Interface Timing Considerations
    6. 4.6  Two-Wire Access to External EEPROM
    7. 4.7  One-Wire Interface Initiated Two-Wire EEPROM Transactions
    8. 4.8  PGA309 Stand-Alone Mode and Two-Wire Transactions
    9. 4.9  PGA309 Two-Wire Bus Master Operation and Bus Sharing Considerations
    10. 4.10 One-Wire Operation with PRG Connected to VOUT
    11. 4.11 Four-Wire Modules and One-Wire Interface (PRG)
  7. 5Application Background
    1. 5.1 Bridge Sensors
    2. 5.2 System Scaling Options for Bridge Sensors
      1. 5.2.1 Absolute Scale
      2. 5.2.2 Ratiometric Scale
    3. 5.3 Trimming Real World Bridge Sensors for Linearity
    4. 5.4 PGA309 Calibration Procedure
  8. 6Register Descriptions
    1. 6.1 Internal Register Overview
    2. 6.2 Internal Register Map
      1. 6.2.1 Register 0: Temp ADC Output Register (Read Only, Address Pointer = 00000)
      2. 6.2.2 Register 1: Fine Offset Adjust (Zero DAC) Register (Read/Write, Address Pointer = 00001)
      3. 6.2.3 Register 2: Fine Gain Adjust (Gain DAC) Register (Read/Write, Address Pointer = 00010)
      4. 6.2.4 Register 3: Reference Control and Linearization Register (Read/Write, Address Pointer = 00011)
      5. 6.2.5 Register 4: PGA Coarse Offset Adjust and Gain Select/Output Amplifier Gain Select Register (Read/Write, Address Pointer = 00100)
      6. 6.2.6 Register 5: PGA Configuration and Over/Under-Scale Limit Register (Read/Write, Address Pointer = 00101)
      7. 6.2.7 Register 6: Temp ADC Control Register (Read/Write, Address Pointer = 00110)
      8. 6.2.8 Register 7: Output Enable Counter Control Register (Read/Write, Address Pointer = 00111)
      9. 6.2.9 Register 8: Alarm Status Register (Read Only, Address Pointer = 01000)
  9.   A External EEPROM Example
    1.     A.1 PGA309 External EEPROM Example
      1.      A.1.1 Gain and Offset Scaling for External EEPROM
      2.      94
  10.   B Detailed Block Diagram
    1.     B.1 Detailed Block Diagram
  11.   C Glossary
  12.   Revision History

6.2.5 Register 4: PGA Coarse Offset Adjust and Gain Select/Output Amplifier Gain Select Register (Read/Write, Address Pointer = 00100)

Bit #D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
Bit Name0WDGO2GO1GO0GI3GI2GI1GI0RFBRFBRFBOS4OS3OS2OS1OS0
POR Value0000000000000000

Bit Descriptions:

OWD: One-Wire Disable (only valid while VOUT is enabled, for use when PRG is connected to VOUT)

1 = Disable
0 = Enable

GO[2:0]: Output Amplifier Gain Select, 1-of-7 plus internal feedback disable

GI[3:0]: Front-End PGA Gain Select, 1-of-8, and Input Mux Control

GI[3] = Input Mux Control
GI[2:0] = Gain Select

RFB: Reserved Factory Bit: Set to zero for proper operation

OS[4:0]: Coarse Offset Adjust on Front-End PGA, 4-bit + sign

1LSB = (VREF)(0.85E − 3)

Table 6-7 Output Amplifier—Gain Select
GO2
[14]		GO1
[13]		GO0
[12]		Output Amplifier Gain
0002
0012.4
0103
0113.6
1004.5
1016
1109
111Disable Internal Feedback
Table 6-8 Front End PGA—Gain Select
GI2
GAIN SEL2
[10]		GI1
GAIN SEL1
[9]		GI0
GAIN SEL0
[8]		Front-End PGA Gain
0004
0018
01016
01123.27
10032
10142.67
11064
111128
Table 6-9 Front End PGA—MUX Select
GI3
MUX CNTL		Input MUX State(1)
0VIN1 = VINP, VIN2 = VINN
1VIN1 = VINN, VIN2 = VINP
(1) VIN1 = Pin 4, VIN2 = Pin 5, VINP = positive input to Front-End PGA, VINN = negative input to Front-End PGA; see detailed block diagram (Figure 8-1).
Table 6-10 Coarse Offset Adjust on Front-End PGA—Data Format Example (VREF = +5V)
OS4
[4]		OS3
[3]		OS2
[2]		OS1
[1]		OS0
[0]		Coarse Offset
(mV)		Coarse Offset
11111−59.5−14(VREF)(0.85E − 3)
11110−55.25−13 (VREF)(0.85E − 3)
11101−51−12 (VREF)(0.85E − 3)
11100−46.75−11 (VREF)(0.85E − 3)
11011−42.5−10 (VREF)(0.85E − 3)
11010−38.25−9 (VREF)(0.85E − 3)
11001−34−8(VREF)(0.85E − 3)
11000−29.75−7 (VREF)(0.85E − 3)
10111−29.75−7 (VREF)(0.85E − 3)
10110−25.5−6 (VREF)(0.85E − 3)
10101−21.25−5 (VREF)(0.85E − 3)
10100−17−4 (VREF)(0.85E − 3)
10101−12.75−3 (VREF)(0.85E − 3)
10010−8.5−2 (VREF)(0.85E − 3)
10001−4.25−1 (VREF)(0.85E − 3)
1000000VREF
0000000VREF
00001+4.25+1 (VREF)(0.85E − 3)
00010+8.5+2 (VREF)(0.85E − 3)
00011+12.75+3 (VREF)(0.85E − 3)
00100+17+4 (VREF)(0.85E − 3)
00101+21.25+5 (VREF)(0.85E − 3)
00110+25.5+6 (VREF)(0.85E − 3)
00111+29.75+7 (VREF)(0.85E − 3)
01000+29.75+7 (VREF)(0.85E − 3)
01001+34+8 (VREF)(0.85E − 3)
01010+38.25+9 (VREF)(0.85E − 3)
01011+42.5+10 (VREF)(0.85E − 3)
01100+46.75+11 (VREF)(0.85E − 3)
01101+51+12 (VREF)(0.85E − 3)
01110+55.25+13 (VREF)(0.85E − 3)
01111+59.5+14 (VREF)(0.85E − 3)