SBOU024C august 2004 – july 2023 PGA309
The PGA309 has a user-accessible test pin (Test, pin 9), which stops the internal state machine cycle and enables the output drive (VOUT) when it is brought high (logic ‘1’). This mode can be used for ease of troubleshooting or initial configuration diagnostics during the system design. During normal (stand-alone) operation, the Test pin must be connected to GND (logic ‘0’).
If the Test pin is brought high at any time, the following happens:
In this mode, a test signal can be applied to the front end of the PGA309, which quickly verifies if the signal path through the PGA309 is functioning correctly.
Test mode (Test pin = high) is recommended during initial calibration because the values in the external EEPROM are ignored and the PGA309 registers can be individually set as desired.