C29x CPU has 4 buses – CPU DR1 (Data Read bus 1), DR2 (Data Read bus 2), DW (Data Write bus) and PR (Program fetch/read bus). Error originating from each bus is detected and captured/logged separately in respective EAM error flag registers for isolating the error source.

In addition to error aggregation, the error events are also segregated into low priority errors and high priority errors. In this example, the error events across all four buses are first segregated into two categories – low priority and high priority based on severity of error and then aggregated. The aggregated outputs – low priority and high priority error events are then passed to ESM. Error priority is pre-defined in the device depending on severity, refer to Error Aggregator Chapter in F29x Technical Reference Manual to know more about error priority for all errors captured in EAM.

Each error has error type value and fixed pre-defined priority assigned to this as shown in the table below taking CPU PR bus as an example.

An example shown in Table 4-1 is for CPU PR bus. Single bit (Correctable error) and WARNPSP errors are classified as low priority errors and all other errors are classified as high priority errors. All high priority error type within CPU PR EAM have single aggregated output similarly for all low priority errors within CPU PR EAM there is one aggregated output.

All high-priority errors from all CPU buses - CPU PR, DR1, DR2 and DW are also combined as CPU HPERR (high priority error) and sent to ESM. Similarly, all low-priority errors from CPU PR, DR1, DR2 and DW are combined as CPU LPERR (Low priority error) and sent to ESM. This is shown in Figure 4-1.

Advantage for the aggregation is that this reduces the number of error events passed to ESM and the corresponding error response configuration in ESM for these error events (captured in the table above) to two error events (high priority and low priority) across all CPU buses. This is redundant to configure each error originating from each CPU bus separately especially when there are several such error events in the device. Hence the error across all the CPU buses are aggregated and provided to ESM. Along with aggregation of errors, segregation is also important since this enables users to configure ESM to generate appropriate action for low priority and high priority errors separately.

Figure 4-1 CPU1 EAM Modules Error Aggregation