SDAA104 September   2025 F29H850TU , F29H859TU-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Error Handling Architecture Overview
  6. 3Example Overview
  7. 4Error Aggregator Overview
    1. 4.1 Error Aggregation
    2. 4.2 Error Logging
    3. 4.3 Error Debugging Using EAM Module
      1. 4.3.1 EAM Error Debugging
      2. 4.3.2 Interpreting Error Address and Program Counter Values
  8. 5Error Signaling Module Overview
    1. 5.1 ESM Error Event Output Configuration and Status Information
      1. 5.1.1 Sysconfig ESM Configuration
    2. 5.2 ESM Error Events Debugging
    3. 5.3 Miscellaneous Debug Tips for ESM
  9. 6BootROM EAM and ESM Error Status
  10. 7FAQ's:
  11. 8Summary
  12. 9References

5.1 ESM Error Event Output Configuration and Status Information

Figure below shows how the respective ESM block can be configured to affect the available output from respective ESM modules. To see further how these outputs are connected to device peripherals refer to ESM subsystem device integration diagram in F29x Technical Reference Manual ESM chapter.

Status Registers listed below are useful in identifying which error event is active and enabled to influence the output from ESM CPU and Sys ESM module:

  1. RAW Status/Set Register (RAW_j) - This indicates if the error event is active where j stands for error event index (j= 0 to 255).
  2. Interrupt Enable Status/Clear Register (STS_j) – This indicates if the error event is active and enabled to influence either low priority or high priority interrupt where j stands for error event index (j= 0 to 255).
ESM CPU Detailed Configuration and Status Info View Figure 5-2 ESM CPU Detailed Configuration and Status Info View
System ESM Detailed Configuration and Status Info View Figure 5-3 System ESM Detailed Configuration and Status Info View